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ORCA(R) ORSPI4
Dual SPI4 Interface and High-Speed SERDES FPSC
October 2007 Data Sheet
Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on a single chip.
Embedded SPI4 Core Features

OIF-SPI4-02.0 compliant interfaces Dynamic timing receive interface: * Full bandwidth up to 450 MHz DDR (900 Mbits/s) for all speed grades. * Bit de-skewing up to 16 phases of the clock * Capable of aligning bit-to-bit skews as large as 1 bit periods Static timing receive interface: * Speeds up to 325 MHz DDR (650 Mbits/s), for all speed grades, including Quarter-Rate mode * Clock aligned or clock centered modes supported DIP-4 and DIP-2 parity generation and checking Transmit Interface: * Speeds up to 450 MHz DDR (900 Mbits/s) * Dedicated LVDS transmit interface for improved data eye integrity * Automatic idle insertion 256 logical ports: * Embedded Calendar-based sequence port polling mechanism and bandwidth allocation. Shadow Calendar support for smooth transition to new Calendar * Up to 32 independent TX and 32 independent RX buffers per SPI4 interface internally. Various aggregation modes to support 1 to 32 separate embedded buffers per TX and RX * Up to 4 independent TX and 4 independent RX clock domain transfers to the FPGA logic FIFO status support modes: * 1/4 rate LVTTL or 1/4 rate LVDS * Automatic status handling or optionally under user control. Credit calculations based on burst size and status are also handled automatically Configuration options as suggested in the OIFSPI4-02.0 standard * Configures parameters such as maximum burst size, calendar length, main and shadow calendars (1K deep each), length of training sequence etc.
Simple FIFO interface to the FPGA logic * Provides ease of design and efficient clock domain transfers Loopback modes provided for system- and chip-level debug Embedded 32-bit internal system bus plus 4-bit parity * Interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded core blocks * Includes built-in system registers that act as the control and status center for the device Low power operation. * Full-rate SPI4.2 interfaces running at 450 MHz DDR (900 Mbits/sec) with dynamic alignment consumes 1.5 W of power or less. More efficient than FPGAs with soft-IP SPI4 solutions which consume in excess of 10 W. Programmable Minburst capability with selectable burst values ranging from 16 to 240. Interoperability demonstrated with ORSPI4 partners. Quad 600 Mbits/s to 3.7 Gbits/s SERDES: * IEEE 802.3ae XAUI (Link State Machine & Alignment FIFOs embedded) * ANSI X3.230:1994 1G/2G FC-compliant (Link State Machine & Alignment FIFOs embedded) * Proven performance (same SERDES used in ORT82G5/ORT42G5 FPSCs) High Performance Memory Controller for interface to external buffer memory * Required for Layer 2 data buffering * QDR II memory interface: - 36-bit Input and 36-bit Output bus, 18-bit address - 175 MHz clock rates - 20+ Gbits/s bandwidth - Supports 2- or 4-word burst mode - Simple FIFO interface to FPGA - Integrated PLL for optimized performance - Proven performance with multiple memory suppliers

Embedded SERDES Core Features
Embedded Memory Controller Features
Note: The term SPI4 refers to OIF SPI-4.2 throughout this document
(c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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ORSPI4_06
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
High-Speed ORCA Series 4 FPGA

Internal performance of > 250 MHz Over 16K programmable logic elements 1.5V operation (30% less power than 1.8 V operation) Comprehensive I/O selections including LVTTL, LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT, DDR, LVDS, bused-LVDS, and LVPECL 1036-pin ftSBGA package provides enough FPGA user I/Os (498) for 4 full-duplex XGMII interfaces, 4 full-duplex PL-3 interfaces, etc; a 40% smaller 1156-pin fpBGA package is available with 356 FPGA user I/Os
Introduction
The SPI4 blocks provide dual 10 Gbits/s physical-to-link layer interfaces in conformance to the OIF-SPI4-02.0 specification. Each block provides a full-duplex interface with an aggregate bandwidth of 13.6 Gbits/s. This is achieved by using 16 LVDS pairs each for RX and TX operating at a maximum data rate of 900 Mbits/s with a 450 MHz DDR clock. Both static and dynamic alignment are supported at the receive interface. Dynamic alignment is used to compensate for bit-to-bit skew at higher data rates, where it becomes difficult to meet tight setup/hold requirements. DIP-4 and DIP-2 parity generation and checking are supported. Data buffering of 8K bytes for both transmit and receive is provided by embedded Dual-Port RAM in each SPI4 core. Internal 1K deep main and shadow calendar supports scheduling of up to 256 ports. The Transmit and Receive Status FIFOs can also store flow control information for up to 256 ports, the maximum specified in the SPI4 specification. An independent QDRII Memory Controller block provides data buffering between the FPGA logic and external memory and supports a throughput of greater than 20 Gbits/s. Data is transferred to and from memory through two sets of 36-bit unidirectional data lines operating at up to 175 MHz DDR. A set of 72 data signals is available to transfer data across the core-FPGA interface and allows the system to utilize the bandwidth available with secondgeneration Quad Data Rate (QDRII) SRAMs. Of the 72 data signals, 8 signals can be either used for parity or data. A soft IP version of this core is also available to allow a second data buffer on this device. The High-Speed SERDES block supports four serial links, each operating at up to 3.7 Gbits/s (2.96 Gbits/s data rate with 8b/10b encoding and decoding), to provide four full-duplex synchronous interfaces with built-in RX Clock and Data Recovery (CDR) and transmitter preemphasis. The SERDES block is identical to that in the ORT82G5 FPSC, supports embedded 8b/10b encoding/decoding and implements link state machines for both 10G Ethernet, and 1G/2G/10G Fibre Channel. The state machines are IEEE P802.3ae/D4.01 XAUI based and also support FC (ANSI X3.230:1994) link synchronization.
Table 1. ORCA ORSPI4 -- Available FPGA Logic
Device ORSPI4 PFU Rows 46 PFU Columns 44 Total PFUs 2,024 FPGA Max User I/O 498/356 LUTs 16,192 EBR Blocks 16 EBR Bits (K) 148 Usable* Gates (K) 471-899
Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFU's are used for logic only (No PFU RAM) with 40% EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFU's are for logic, 20% are used for PFU RAM, with 80% EBR usage and 4 PLL's. The ORSPI4 device is offered in two packages: 1036 ftSBGA and 1156 fpBGA. The 1036 package offers 498 FPGA User I/Os while the 1156 package offers 356 FPGA User I/Os. Additionally, the SERDES option is not available on the 1156 package.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
ORSPI4 Overview
The ORSPI4 FPSC provides two SPI4.2 interface blocks, a Memory Controller and a 4-channel SERDES block, combined with FPGA logic. Based on the 1.5 V OR4E06 ORCA FPGA, it has a 46 x 44 array of Programmable Logic Cells (PLCs). The embedded core is attached to the right side of the device, as shown below, and is integrated directly into the FPGA array. A top level diagram of the basic chip configuration is shown in Figure 1.
Figure 1. ORSPI4 Basic Chip Configuration
Memory Controller I/O Serial I/O / SPI4 I/O SPI4 I/O
Embedded Core Memory Controller FPGA Programmable I/O
SPI4.2 I/F
ORCA 4E06-Based Programmable Logic
SPI4.2 I/F
Shared I/O
Quad SERDES
Each of the logic blocks in the embedded core is functionally independent from the other blocks. Connections between blocks must be made through the FPGA logic. However, one of the SPI4 blocks and the SERDES block share I/Os. Hence the device may be configured to provide either two SPI4 interfaces or one SPI4 interface and one serial interface.
What Is an FPSC?
FPSCs, or Field-Programmable System Chips, are devices that combine field-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the design effort savings of soft Intellectual Property (IP) cores, and the speed, design density, and economy of ASICs.
FPSC Overview
Lattice's Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of Programmable Logic Cells are integrated with an embedded logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 area efficiency, none of the FPGA functionality is changed--all of the Series 4 FPGA capability is retained including the Embedded Block RAMs, MicroProcessor Interface (MPI), boundary scan, etc. Pins from the replaced columns of programmable logic are used as I/O pins for the embedded core. The remainder of the device pins retain their FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates. Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater number of interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and accounted for in the ispLEVER Development System. Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-master 32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic functions including the Embedded Block RAMs and the microprocessor interface. Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the FPGA as a system. For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC configuration manager, and compiled Verilog simulation models, HSPICE and/or IBIS models for I/O buffers, and complete online documentation. The kit's software coupled with the design environment, provides a seamless FPSC design environment. More information can be obtained by visiting the Lattice website at http://www.latticesemi.com.
SPI4 Protocol Overview
The System Packet Interface Level 4, Phase 2 (SPI4) was defined by the Optical Internetworking Forum (OIF) as an interface for packet and cell transfers between a Physical Layer (PHY) device and a link layer device for applications requiring up to 10 Gbit/s aggregate bandwidth. The system level model for the SPI4 interface is shown in Figure 2.
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Figure 2. System Model for SPI4 Interface Link Layer in Model
TSTAT[1:0] TSCLK
ORCA ORSPI4 Data Sheet
PHY Layer in Model
Transmit Link Layer Device
TDCLK TDAT[15:0] TCTL
Physical (PHY)
Layer Device
RSTAT[1:0] RSCLK
Receive Link Layer Device
RDCLK RDAT[15:0] RCTL
The details of the interface are specified in the OIF document "Implementation Agreement OIF-SPI4-02.0" (www.oiforum.com). That specification is based on the system model shown in the previous figure, which, in turn, is based on the Open System Interconnect (OSI) reference model. In the system model, a "transmit interface" sends address, start and end of packet signals and error control information from a Link Layer device to a PHY device and receives flow control (status) information from the PHY device. In the other direction, a "receive interface" at the Link Layer receives data from a PHY device and sends status information to the PHY device. While this convention provides a clear framework for defining the system level functions, a clean separation between Link Layer and Physical Layer functionality is not often seen in actual implementations. The ORSPI4 FPSC SPI4 blocks implement the basic functions defined in the standard and also implements additional options, as suggested in the standard, to configure parameters such as maximum burst size, calendar length, length of training sequence, etc. As required by the specification, the transmit and receive interfaces operate completely independently.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Embedded Core Overview - Functions and Features
The embedded core contains four separate functional blocks, two SPI4 interface blocks, a high-speed Memory Controller block, and a quad SERDES block providing 4 channels of 0.6-3.7 Gbits/s SERDES. Features common to all blocks include: * Improved PowerPC (R) 860 and PowerPC II high-speed synchronous MicroProcessor Interface that can be used for configuration, readback, device control, and device status; as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space provided. * New embedded AMBA TM specification 2.0 AHB system bus (ARM (R) processor) facilitates communication among the MicroProcessor Interface, configuration logic, and embedded core blocks. * FPSC Design Kit available for use with ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthesis, simulation, and timing analysis.
SPI4 Interface Blocks - Overview
The ORSPI4 FPSC provides two independent SPI4 interface blocks in the embedded core. The two SPI4 blocks are identical and the following overview applies to both blocks. In the following sections, the SPI4 protocol conventions for "transmit" and "receive" are not followed, since in various applications the ORSPI4 FPSC could be used to perform different functions at various levels in the SPI4 protocol stack. Instead, the "transmit" functions are those used to transmit data to and receive current status information from the device at the other end of the SPI4 link. The "receive" functions are those used to receive data from and transmit current status information to the device at the other end of the SPI4 link. Each SPI4 block supports a standard 10 Gbits/s physical-to-link layer interface in conformance to the specification. This is achieved by using 16 LVDS pairs each for RX and TX that operate at a maximum data rate of 900 Mbits/s with a 450 MHz DDR clock. Data buffering of 8 Kbytes each in the transmit and receive direction (example: 256 bytes each for up to 32 ports) is provided by embedded Dual-Port RAM (DPRAM). Aggregation of buffer space is supported for systems with less than 32 ports. The internal calendar and Transmit and Receive Status FIFOs have been sized so that applications with larger numbers of ports can be supported. The ORSPI4 has been designed to support up to 256 ports, the maximum specified in the SPI4 specification. Despite operating independently, both the transmit path and the receive path logic perform similar functions and the partitioning of both logical blocks are quite similar as shown in Figure 3. The top level partitioning is between the logic blocks to transfer and process data and control information, and the logic blocks to generate, transfer and process status information. SPI4 Interface Block Features * Each SPI4 block provides a standard 10 Gbits/s physical-to-link layer interface in conformance to the OIF-SPI402.0 specification. Each interface provides an aggregate bandwidth of 13.6 Gbits/s. This is achieved by using 16 LVDS pairs each for RX and TX with a maximum data rate of 900 Mbits/s using a 450 MHz DDR clock. * The blocks can be used for applications such as interconnecting an OC-192 framer with a proprietary packetized interface, to a network processor with a SPI4 based packet interface or vice versa. * Support for "static" or "dynamic" alignment at the receive interface. At clock rates above 350 MHz DDR, it becomes difficult to meet the tight setup/hold requirements at the receiver using static alignment. In this case, dynamic alignment is used to compensate for bit-to-bit skew. * Dynamic alignment automatically compensates for Process, Voltage, and Temperature (PVT) changes in devices and systems. - Full bandwidth up to 450 MHz DDR (900 Mbits/s throughput) - Dynamically performs alignment based on 16 phases of the RX clock for improved accuracy - Alignment algorithm can be done based on excessive bit errors on the DIP-4 calculation - Clock skews up to +/- one clock cycle can be compensated by the dynamic alignment logic
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
* For low speed data, static alignment can be selected through a programmable control bit - Speeds up to 350 MHz DDR (700 Mbits/s throughput) - Dynamic alignment is bypassed and disabled to save power in static alignment mode. - Programmable on-edge or on-center clock/data relationship option at receiver. - Programmable clock delay * Single-link and multi-link operation. * SPI4 transmit data protocol support logic - Combines the data and control words from the transmit FIFO (DPRAMs) into the SPI4 format - Performs DIP-4 calculation over data and control words on the TX side and inserts into the payload control word * Handles all credit calculations based on the status information automatically * Provides optional signals to FPGA interface logic for flow control: - Current transmit Port ID (Calendar Port or user specified port # per calendar port) - Current BURST_VAL Parameter for that Port - Status from that Port * Embedded Calendar-based port polling sequence mechanism and bandwidth allocation for all 256 ports - Programmable transmit and receive calendar tables support up to 256 ports * Two calendars are supported in each direction - Main Calendar (1K deep) - Shadow Calendar (also 1K deep). User can reconfigure second calendar while operating off main calendar, and then switch on the next cycle to allow hitless operation - All calendar configuration parameters specified in the standard (CALENDAR_LEN, CALENDAR_M, etc.) are supported * Transmit and Receive Status FIFOs provided to store flow control information for up to 256 ports. - Performs Status frame creation - DIP-2 odd parity calculated over the status frames - Supports either quarter-rate LVDS or LVTTL status channels * Support for various options for flow control status creation, selectable per port: - Based on DPRAM FIFO fill levels - Based on status from FPGA interface per port - Both of the above * Dual-port RAM interface to the FPGA supports flexible data widths for both the receive and transmit FPGA/core interfaces. - Scalable data bus enables users to configure TX interface for their respective port bandwidth requirements - A total of 4 DPRAM banks where each of the DPRAMs can be logically partitioned into 1, 2, 4, or 8 virtual FIFOs - Used for temporary storage and clock domain crossing - Can be configured to provide 32-, 64-, 128-bit data bus interfaces from the FPGA (plus accompanying control signals) - 32-bit mode: Four banks are separate and accessed independently - 64-bit mode: Banks 0 & 1 become a single aggregation and Banks 2 & 3 become a single aggregation - 128-bit mode: All four banks become a single aggregation - Mixed mode: One 64-bit (two banks become a single aggregation) and two banks are separate and accessed independently * Training pattern generation - User controlled "alpha" repetitions of training pattern in TX_DATA_MAX_T intervals - Automatic generation of training pattern during loss of synchronization
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* Automatic idle generation - When no data for a given channel is available for transmit - If the receiver on other end of the link is "satisfied" for this channel * Automatic training pattern and idle deletion in receive path
ORCA ORSPI4 Data Sheet
* Low-power, high performance ASIC LVDS I/Os compliant with EIA(R)-644 - I/O buffers support hot insertion - I/O buffers proven to operate at over 900 MHz rates (Lattice ORLI10G FPSC uses same LVDS buffers) - On-chip center tap termination for common mode noise reduction * Configuration options as suggested in the OIF-SPI4-02.0 standard are supported to configure parameters such as maximum burst size, calendar length, length of training sequence, etc. * Support for three forms of loopback: - High-speed near end loopback which involves looping back data from the high-speed transmit block serial output to the high-speed receive block serial input. All of the logic up to the LVDS buffers is included in the loopback path. The LVDS buffers are bypassed - Far end loopback which involves looping back the 128-bit output data from high-speed receive block to the 128-bit input of the high-speed transmit block. Data is received at the high-speed SPI4 RX interface and transmitted at the SPI4 TX interface. The transmit protocol, receive protocol and DPRAM blocks are bypassed. This works for both static and dynamic alignment modes. - Low-speed near end loopback which excludes the high-speed blocks from the loopback path. This involves sourcing data from the FPGA, looping back the output of the transmit protocol block into the receive protocol block and observing data at the core-FPGA boundary * Support for several SPI4 debug options: - Under software control, DIP-4 errors can be forced by inverting the DIP-4 parity bits - DIP-2 errors can be forced by inverting the DIP-2 parity bits - Eight-bit counters are provided for counting DIP-4 and DIP-2 errors * SPI4 Status Reporting Capabilities: - Status information is reported through status registers. - Most conditions can also cause an alarm (interrupt) to be generated - DIP-4, DIP-2 errors - Deskew error from high-speed RX side - DPRAM Virtual FIFO overruns
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Lattice Semiconductor
Figure 3. ORSPI4 SPI4 Interface Block - Top Level Functional Partitioning
Transmit Status
ORCA ORSPI4 Data Sheet
Transmit SPI4 Logic - Status Read Control Sequencer
Port Calendar Address Map Descriptor
TSTAT[1:0]
Protocol
Input
TSCLK
32, 64, Transmit Data 128
Transmit Buffers
SPI4 Logic - Data
TDCLK
Transmit Control FIFO_FULL
Write Control
DPRAM Banks
Protocol
Output
TDAT[15:0] TCTL
Receive Status
Receive Transmit Buffers
Address Port Map Descriptor Port Status Sequencer Calendar
SPI4 Logic - Status
Protocol
RSTAT[1:0]
Output
RSCLK
Receive Buffers
Read Data
128
SPI4 Logic - Data
RDCLK
Read Control
ReceiveDPRAM Write Center Banks Control
Protocol
Input
RDAT[15:0] RCTL
At the embedded core/FPGA interface, data buffering is provided by banks of DPRAM partitioned into FIFOs. FIFO reads and writes are completely decoupled. Data and accompanying address, packet delineation and error identification information are written into the selected FIFO as received - either from the FPGA, in the transmit case, or from the receive link. For transmit, reads are performed from the FIFOs based on pre-programmed packet format information, a pre-programmed schedule for link access as read from calendar logic, and far end status information as received from the transmit status logic. In the receive direction, the receive status logic transmits information concerning the states of the receive buffers on the receive status links, while the FPGA logic reads data from the FIFOs as needed under control of the FPGA logic. The read/write control functions are similar if operating with external RAM. In this case, the internal DPRAM can be used as clock domain crossing FIFOs. Formatting/deformatting, flow control processing, and error control logic forms the interface between the DPRAM banks and the SPI4 transmit and receive blocks. This logic performs the necessary conversions between the SPI4 and FPGA/core interface formats. It also performs DIP-2 (status) and DIP-4 (control) generation/checking. Finally, the SPI4 interface blocks perform the MUX/DEMUX functions for rate conversion between the internal core data paths and the SPI4 links and also provides the needed LVDS driver and receiver functions. Either static or dynamic alignment is available at the receiver interface. Dynamic alignment is used to compensate for bit-to-bit skew at higher data rates where it becomes difficult to meet tight setup and hold timing requirements.
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Lattice Semiconductor SPI4 Transmit Path Overview
ORCA ORSPI4 Data Sheet
The first of the major blocks in the Transmit section contains four DPRAM banks which can be configured to provide 32-bit, 64-bit or 128-bit data bus interfaces from the FPGA to the embedded core. Providing a scalable data bus enables users to tailor the transmit interface to meet their port bandwidth requirements. For example, with a POSPHY Level 3 (PL3) interface supporting multiple PHYs (ports), a single 32-bit interface to the Transmit DPRAM is required. For an Ethernet 10 Gbits/s interface, a single port will require a single 128-bit interface to the Transmit DPRAM. To realize the various data bus interfaces or aggregation modes, the user must configure the mode within the embedded core via the MPI interface or the system bus. Multiple DPRAM banks can be aggregated into larger FIFOs. Division of the DPRAM banks into virtual partitions (up to eight) is also possible. The FPGA logic initiates a write to DPRAM by providing Data, Port ID, 3-bit FIFO Address and Write Enable signals to the SPI4 block. The internal FIFO controller latches the data and port control information into a temporary hold register that stores the data until an entire 128-bit line is captured, or an EOP is asserted. The 128-bit line is then written into the selected virtual FIFO. Associated with each FPGA data write interface, there are also control information signals and a transmit clock. The FIFO control logic transparently passes the control information to the Control memory, with the exception of the Byte Enable bits (BE[3:0]), which indicate which bytes of the associated 32-bit Word are valid. The DPRAM read logic blocks poll port data from the DPRAM banks, based on a preconfigured calendar sequence and the current status of each active port. The SPI4 calendar is a mechanism that maintains out-of-band statistics of the current status of each port supported across the SPI4 interface. The calendar is a reverse direction flow-control mechanism used to control the dynamic bandwidth allocated for the each supported port. By periodically providing far end receive status for each port, the transmitter can modulate the amount of bandwidth allocated to a particular port dynamically. Writes to the DPRAMs from the FPGA logic are asynchronous to the calendar polling algorithm. The SPI4 transmit logic reads data from the DPRAMs according to a strict calendar sequence algorithm and will generally not read port data from the virtual FIFOs in the sequence it was written. Both a main and a shadow calendar are provided and are each 1K deep. This enables the user to provide finer granularity of the polling sequence based on bandwidth allocated for each port. The length of the calendar table (CALENDAR_LEN) is programmable. CALENDAR_LEN should be at least as large as the number of active ports (channels) in the system and should not exceed the upper threshold set by the parameter (MAX_CALENDAR_LEN). There are two basic modes supported for transmitting data. Within the SPI4 core, the embedded core operates identically for all modes. At the FPGA interface, processing will be done slightly differently, depending upon the mode the user requires. Each mode is discussed below. * Embedded memory mode - This mode is used when the ORSPI4 is interfacing to asynchronous FPGA interfaces, such as POS-PHY Level 3, 1GbE, Utopia Level 3, etc. and storing the data in the virtual DPRAM FIFOs. When operating in this mode, the SPI4 transmit logic will read port data from the FIFOs according to the calendar sequence. If there is no data, it will send idle data and advance to the next port. It is the user's responsibility to ensure the proper port data has been written to the virtual FIFO. * External memory mode - This mode is used in conjunction with the Memory Controller or some other external memory based interface where data is available only after some fixed delay. In this mode the SPI4 transmit logic instructs the FPGA as to what port data to retrieve as well as how many bursts of data to retrieve. The FPGA is responsible to write the data read from the Memory Controller into the DPRAMs. Data is read from the DPRAM devices by the SPI4 transmit logic according to the transmit calendar. The DPRAM read logic also includes a Port Descriptor Memory (PDM) which is a user configurable memory containing a list of read control parameters for all enabled ports to be polled. The depth of the memory is 256 locations,
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
which corresponds to the maximum number of ports that are supported by SPI4. The PDM data is comprised of three separate segments - a 10-bit dynamic table maintained by the SPI4 logic, a static 20-bit table, and a dynamic 3-bit register file written by the FIFO Status Update (FSU) logic. The PDM provides a mapping of the SPI4 port number to the FPGA interface device/port number, removing the burden from FPGA logic. When port data is read from the PDM, a status update bit (the U-bit) is first examined to see whether the STAT field is new or stale. If stale, then the STAT field is not considered for the rest of processing. If the STAT field is new (Ubit=1) the STAT field is used in conjunction with other field to calculate what the new Credit field for the port should be. A SATISFIED status indicates the corresponding port's FIFO is almost full, and only transfers using the remaining previously granted 16-byte blocks (if any) may be sent to corresponding port until the next status update. No additional transfers to that port are permitted. When a HUNGRY status indication is received, transfers up to MAXBURST2 16-byte blocks or the remainder of what was previously granted (whichever is greater), may be sent to the corresponding port prior to the next status update. A STARVING status indication indicates that buffer underflow is imminent in the corresponding PHY port. When STARVING is received, transfers for up to MAXBURST1 16-byte blocks may be sent to the corresponding port prior to the next status update. If the U-bit is cleared, this indicates the STAT field has already been used to update the Credit field on a previous Port servicing. Therefore, the Credit field should simply be reduced by BURST_VAL. Otherwise, the Credit field is updated to the new Credit value minus BURST_VAL. In both cases, the output of the logic is used to update the Credit field. If the Credit field is zero, and the STAT field is stale, then the port receives no service. Read accesses of the port control information need to be optimized to minimize any lost bandwidth due to the Credit field having a value of zero. Data read from the DPRAMS is sent to the SPI4 transmit block which is responsible for the following functions: * Combining the data and control words from the Transmit FIFO into the data format specified in the OIF SPI4 standard. * DIP-4 calculation and insertion into the payload control word. * Generation of idle/training control words in programmable intervals. Training words are used to dynamically align the far end receiver. As long as a disabled status `11' is received on the SPI4 status channel, the transmit interface block sends continuous training patterns (10 training control words followed by 10 training data words). When valid status is received on the status channel, user data is normally sent on the SPI4 data link. However, users can also periodically schedule training patterns in TX_DATA_MAX_T periods. The training patterns can be repeated TX_ALPHA times. Both TX_ALPHA and TX_DATA_MAX_T are programmable control register bits. The SPI4 transmit block contains the high-speed serializer which uses the x8 clock, synthesized by an internal PLL, to generate the high-speed data from the low-speed 128-bit FIFO data. Data is transmitted off-chip using a 16-bit LVDS data bus - TDAT[15:0], a LVDS control bit - TCTL, and a source synchronous clock - TDCLK. The 16-bit data bus and control are DDR with respect to TDCLK. In order to support 10 Gbits/s throughput, the minimum frequency of TDCLK needs to be 622 Mbits/s (311 MHz DDR). To allow considerable margin above this minimum data rate a maximum frequency of operation of 900 Mbits/s is supported. The Transmit Status Protocol (S4TSP) block provides the interface to the SPI4 Transmit Status interfaces. These signals can be either LVDS or LVCMOS buffers. The S4TSP block is responsible for the following functions: * FIFO Status Decoding and Buffering. * Framing using the status framing pattern. * DIP-2 checking of incoming status information. 11
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
The FIFO Status Update logic block reads the Port and Status information and uses this information to update Port Descriptor Memory STAT field. Whenever a valid STAT field has been updated, the associated U-bit field is set as discussed previously. This indicates that the STAT field is new and that the Credit field for that must be re-evaluated the next time it is selected as a source for transmit data.
SPI4 Receive Path Overview
In the receive direction, data is received in SPI4 format on the LVDS I/Os at the receive interface. The data is written into DPRAM as received and read from the DPRAMs as requested by the FPGA logic. Control information is also interpreted and buffered and idles and training sequences are removed from the incoming data stream. Receive FIFO status is transmitted from the Receive Status interface according to a pre-configured polling sequence contained within the Receive Calendar. Data is formatted into the SPI4 Receive Status format and sent to the physical links as either LVDS or LVTTL signals. The SPI4 block contains the high-speed receive logic. Incoming LVDS signals, in SPI4 format, include the 16-bit data bus (RDAT[15:0]), a control bit (RCTL) and a source synchronous DDR clock (RDCLK). The incoming data is deserialized to a 128-bit format and the control information is converted to an 8-bit format. The SPI4 receive block also detects training patterns and performs dynamic alignment of the incoming data. At speeds above 700 Mbit/s (350 MHz) it becomes necessary to use dynamic alignment. Skews of up to one clock period can be compensated by the dynamic alignment logic. For low speed incoming data, static alignment can be chosen through a programmable control bit. Various timing options of receive data vs. receive clock are also programmable. The SPI4 block is responsible for decoding the in-band control information. It then forwards both the data and control information, such as link address, SOP, EOP and error, to the virtual FIFOs. The SPI4 block also parses the control words embedded within the incoming data. Using this control information, it performs the following functions: * Checks DIP-4 parity * Monitors for continuous alignment (if more than a programmable number of DIP-4 parity errors exist, there may be an alignment problem). * Removes idle/training words. * Extracts link address and SOP, EOP and valid packet (no error) signals. In the receive direction there are also four Dual Port Memory (DPRAM) banks that contain a total of 8K bytes available for clock domain crossing and/or temporary buffering. As with the transmit buffers, each bank can be further partitioned up to 8 virtual memories, one for each of 8 ports. The following are the characteristics of the DPRAM virtual FIFOs: * The DPRAM memories support asynchronous reads. Each DPRAM bank can be accessed on the FPGA side with an individual clock. * For data buffering beyond 32 ports, the DPRAM banks can be used as clock domain crossing FIFOs before writing the data and control information into an external memory. If fewer ports are supported, the virtual memories can be aggregated, providing more buffer space for each port. * Each DPRAM bank has a 32-bit data and 8-bit control read interface to the FPGA. When using the DPRAM memories, the data can be read as either a 32-, 64-, or 128-bit data bus with associated control signals. * At any time, the user can poll the status of a FIFO within a DPRAM bank by providing just the read address without a valid read enable. * A FIFO empty flag is generated by the read control logic to the FPGA. This empty flag can be programmed to indicate truly empty or < 1/4 full (1/4 full - 1).
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
In addition to formatting received data and sending it to the FPGA logic, the receive block also sends status information to the SPI4 status interface. The Port Status Sequencer (PSS) block is responsible for providing port status to the SPI4 Receive Status block logic according to a pre-configured calendar sequence. Status is derived from the fill-levels of the DPRAM FIFOs and/or from the FPGA status interface. The SPI4 Receive Status block is responsible for FIFO status encoding, calendar management, status pattern encoding (sync bits "11"), DIP-2 calculation and optional calendar selection word encoding. The SPI4 Receive Status block contains the low speed LVTTL output buffers and LVDS output buffers necessary for the output stage of receive status logic. The option to choose between LVTTL or LVDS outputs is done by setting a control register bit. SPI4 Debugging and Statistics Gathering Support There are also several other features, including three loopback modes incorporated into the embedded core to assist in debugging and statistic gathering. These features involve both the transmit and receive paths. The three forms of loopback supported directly are: * High-speed near-end loopback * Far-end high-speed loopback * Low-speed near-end loopback The SPI4 blocks support the following error insertion and status reporting options for testing: * DIP-4 odd parity is calculated over data and control words and inserted on the TX side. DIP-4 errors can be forced by inverting the DIP-4 parity bits. DIP-4 parity is then checked at the receive interface. * DIP-2 odd parity is calculated over the status frames and inserted on the RX side. DIP-2 errors can be forced by inverting the DIP-2 parity bits. DIP-2 parity is then checked at the transmit status interface. * Eight-bit counters are provided for counting DIP-4 and DIP-2 errors. * Deskew error reporting for high-speed RX side dynamic alignment. This can cause an alarm. * DPRAM FIFO overrun reporting. These can cause an alarm.
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Lattice Semiconductor Memory Controller - Overview
ORCA ORSPI4 Data Sheet
The Memory Controller block controls an interface to external Quad Data Rate (QDRII) SRAM for data buffering between the FPGA logic and external memory. The key features of the Memory Controller interface are described below: Memory Controller Features * Independent Memory Controller interface to external Quad Data Rate (QDRII) SRAMs from multiple suppliers for data buffering. - Provides additional packet buffering for > 32 ports - Provides traffic smoothing for any number of ports * The Controller supports a throughput of greater than 20 Gbits/s so that all the data received on the SPI4 interface at 10 Gbits/s can be buffered. * The QDRII SRAM supports this throughput with 36 unidirectional data lines in both the read and write directions. * The controller block provides the ability to access external QDRII SRAM through the FPGA. - A set of 72 data signals across the core-FPGA interface - Of the 72, 8 signals can be either used for parity or data. - Simple asynchronous FIFO interface to FPGA for ease of design. A high-speed clock signal is provided to the FPGA as an option to make the write and read synchronous, if desired. * The core passes the data transparently to and from the QDRII SRAM in two-word or four-word bursts. Interfaces to memory are 36 bits wide and the address buses are 18 bits wide. - Supports the interfaces required for a 512K x 36 bit (18 Mbit) QDRII SRAM in two-word burst mode. - Only 17 address lines are required in four-word burst mode. * Status/Alarm reported to user through registers - Data length mismatch from the write controller state machine - Data instruction coherency error - Write data, Read data FIFO overrun and underrun errors * Additional high-speed Memory Controller can be implemented in FPGA gates if required.
SERDES Logic Block - Overview
The SERDES logic block in of the ORSPI4 contains four Clock and Data Recovery (CDR) macrocells and four Serializer/Deserializer (SERDES) macrocells to support four channels of 8b/10b (IEEE 802.3.2002) encoded serial links. The logic block also contains Fiber Channel and XAUI-based state machines, logic to support multi-channel alignment and MUX/DEMUX logic for the FPGA/core interface. Figure 4 shows the SERDES top level block diagram and the basic data flow. Boundary scan for the SERDES only includes programmable I/Os and does not include any of the embedded block I/Os.
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Lattice Semiconductor
Figure 4. SERDES Top Level Block Diagram.
ORCA ORSPI4 Data Sheet
0.6 Gbits/s TO 3.7 Gbits/s DATA STANDARD FPGA I/Os
ORCA SERIES 4 FPGA LOGIC
BYTE- SERDES w/ 8b/10b WIDE CLOCK/DATA DECODER/ENCODER DATA RECOVERY 4:1 MUX/1:4 DEMUX
CML I/Os
4 FULLDUPLEX SERIAL CHANNELS
0.6 Gbits/s TO 3.7 Gbits/s DATA
The serial channels can each operate at up to 3.7 Gbits/s (2.96 Gbits/s data rate) with a full-duplex synchronous interface with built-in clock recovery (CDR). The 8b/10b encoding provides guaranteed ones density for the CDR, byte alignment, and error detection. The core is also capable of frame synchronization and physical link monitoring. An overview of the individual blocks in the embedded core is presented in the following paragraphs. The SERDES portion of the core contains a quad transceiver block for serial data transmission at a selectable data rate of 0.6 to 3.7 Gbits/s. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core blocks and high-speed CML interfaces to the serial links. Serializer and Deserializer (SERDES) The SERDES portion of the core contains a transceiver block for serial data transmission at a selectable data rate of 0.6-3.7 Gbits/s. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core blocks and high-speed CML interfaces to the serial links. The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts highspeed (up to 3.7 Gbits/s) serial data. Based on data transitions, the receiver locks an analog receive PLL for each channel to retime the data, then demultiplexes the data down to parallel bytes and an accompanying clock. The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.7 Gbits/s serial data for offchip communication. The transmitter generates the necessary clocks from a lower speed reference clock. The transceiver is controlled and configured through the system bus in the FPGA logic and through the external 8bit microprocessor interface of the FPGA. Each channel has associated dedicated registers that are readable and writable. There are also global registers for control of common circuitry and functions. The SERDES performs 8b/10b encoding and decoding for each channel. The 8b/10b transmission code can support either Ethernet or Fibre Channel specifications for serial encoding/decoding, special characters, and error detection. The user can disable the 8b/10b decoder to receive raw 10-bit words, which will be rate reduced by the SERDES. If this mode is chosen, the user must also bypass the multichannel alignment FIFOs. The SERDES macrocell contains its own dedicated PLLs for both transmit and receive clock generation. The user provides a reference clock of the appropriate frequency. The receiver PLLs extract the clock from the serial input data and re-time the data with the recovered clock. MUX/DEMUX Block The MUX/DEMUX logic converts the data format for the high-speed serial links to a wide, low-speed format for crossing the CORE/FPGA interface. The intermediate interface to the SERDES macrocell runs at 1/10th the bit
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
rate of the data lane. The MUX/DEMUX converts the data rate and bus width so the interface to the FPGA core can run at 1/4th this intermediate frequency, giving a range of 25.0 to 92.5 MHz for the data rates into and out of the FPGA logic. Multi-Channel Alignment FIFOs In the ORSPI4 SERDES block, the four incoming data channels can be independent of each other or can be synchronized in several ways. Two channels within a SERDES block can be aligned together; channels A and B and/or channels C and D. Finally, four channels in a SERDES block can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. XAUI and Fibre Channel Link State Machines Two separate link state machines are included in the architecture. A XAUI-based link state machine is included in the embedded core to implement the IEEE 802.3ae standard. A separate state machine for Fibre Channel is also implemented. FPGA/Embedded Core Interface In 8b/10b mode, the FPGA logic will receive/transmit 32-bits of data (up to 92.5 MHz) and four K_CTRL bits from/to the embedded core. There are 4 data streams in each direction plus additional timing, status and control signals. Data sent to the FPGA can be aligned using comma (/K/) characters or /A/ character as specified either by Fibre Channel or by IEEE 802.3ae for XAUI based interfaces. The alignment character is made available to the FPGA along with the data. The special characters K28.1, K28.5 and K28.7 are treated as valid comma characters by the SERDES. If the receive channel alignment FIFOs are bypassed, then each channel will provide its own receive clock in addition to data and comma character detect signals. If the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in 8b/10b bypass mode. SERDES Features * Four channels of 0.6-3.7G SERDES with 8b/10b encoding/decoding are supported. The SERDES quad is IEEE P802.3ae/D4.01 XAUI based and also supports the FC (ANSI X3.230:1994) link synchronization state machine specification. * The high-speed SERDES are programmable and support serial data rates including 622 Mbits/s, 1.0 Gbits/s, 1.25 Gbits/s, 2.5 Gbits/s, 3.125 Gbits/s, and 3.7 Gbits/s. Operation has been demonstrated on design tolerance devices at 3.7 Gbits/s across 26 in. of FR-4 backplane and at 3.2 Gbits/s across 40 in. of FR-4 backplane across temperature and voltage specifications. * Asynchronous operation per receive channel, with the receiver frequency tolerance based on one reference clock per four channels (separate PLL per channel). * Ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control registers. * Programmable one-half amplitude transmit mode for reduced power in chip-to-chip application. * Transmit preemphasis (programmable) for improved receive data eye opening. * 32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in FPGA logic. * Provides a 10 Gbits/s backplane interface to a switch fabric using four 2.5 Gbit/s links. Also supports port cards at 2.5 Gbit/s. * 3.125 Gbits/s SERDES compliant with XAUI serial data specification for 10 Gigabit Ethernet applications. * Most XAUI features for 10 Gigabit Ethernet are embedded including the required link state machine. * Compliant to Fibre Channel physical layer specification.
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ORCA ORSPI4 Data Sheet
* High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks. * Four-channel HSI functions provide 2.96 Gbits/s serial user data interface per channel (8b/10b encoding and decoding) for a total chip bandwidth of > 10 Gbits/s (full duplex). * SERDES have low-power CML buffers and support 1.5 V or 1.8 V I/Os. This allows use of the SERDES with optical transceiver, coaxial copper media, shielded twisted pair wiring or high-speed backplanes such as FR-4. * Powerdown option of SERDES HSI receiver or transmitter is on a per-channel basis. * Automatic lock to reference clock in the absence of valid receive data. * High-speed and low-speed loopback test modes. * No external components required for clock recovery and frequency synthesis. * Built-in boundary scan (IEEE (R) 1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES interface. * FIFOs can align incoming data either across groups of four channels or groups of two channels. Alignment is done either using comma characters or by using the /A/ character in XAUI mode. Optional ability to bypass the alignment FIFOs for asynchronous operation between channels (Each channel includes its own clock and frame pulse or comma detect).
ORSPI4 FPGA Logic Overview
The following sections provide a brief overview of the main architectural features of the ORSPI4 FPGA logic. For more detailed information, please refer to the ORCA Series 4 FPGA Data Sheet which can be found under the "Products" folder on the Lattice Semiconductor main Web site: www.latticesemi.com. The ORCA Series 4 FPGA Data Sheet provides detailed information required for designing with the ORSPI4 device. Topics covered in the ORCA Series 4 Data Sheet include: * FPGA Logic Architecture * FPGA Routing Resources * FPGA Clock Routing Resources * FPGA Programmable Input/Output Cells (PICs) * FPGA Embedded Block RAM (EBR) * Microprocessor Interface (MPI) * Phase-Locked Loops (PLLs) * Electrical Characteristics * FPGA Timing Characteristics * Power-up * Configuration
ORCA Series 4 FPGA Logic Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge of FPGA and ASIC designs. Modular hardware and software technologies enable System-on-Chip integration with true plug-and-play design implementation. The architecture consists of the following basic elements: Programmable Logic Cells (PLCs), Programmable I/O cells (PIOs), Embedded Block RAMs (EBRs), plus supporting system-level features. These elements are interconnected with a rich routing fabric of both global and local wires. An array of PLCs is surrounded by common interface blocks that provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. Each PLC contains a Programmable Function Unit (PFU), Supplemental Logic Interconnect Cell (SLIC), local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. Large blocks of 512 x 18 quad-port RAM complement the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the MPI, PLLs, and the Embedded System Bus (ESB).
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Lattice Semiconductor Programmable Logic Features
ORCA ORSPI4 Data Sheet
* High-performance programmable logic: - 0.16 m, 7-level metal technology. - Internal performance of >250 MHz. - Over 600K usable system gates. - Meets multiple I/O interface standards. - 1.5 V operation (30% less power than 1.8 V operation), translates to greater performance. * Traditional I/O selections: - LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os. - Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. - Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. - Two slew rates supported (fast and slew-limited). - Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time. - Fast open-drain drive capability. - Capability to register 3-state enable signal. - Off-chip clock drive capability. - Two-input function generator in output path. * New programmable high-speed I/O: - Single-ended: GTL, GTL+, PECL, SSTL3/2 (Class I and II), HSTL (Class I, III, IV), ZBT, and DDR. - Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable, (on/off) internal parallel termination (100 ) is also supported for these I/Os. * New capability to (de)multiplex I/O signals: - New DDR on both input and output at rates up to 350 MHz (700 Mbits/s effective rate). - New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). * Enhanced twin-quad Programmable Function Unit (PFU): - Eight 16-bit Look-Up Tables (LUTs) per PFU. - Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. - New register control in each PFU has two independent programmable clocks, clock enables, local SET/RESET, and data selects. - New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 1 MUX, new 8 1 MUX, and ripple mode arithmetic functions in the same PFU. - 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers. - Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed. - Flexible fast access to PFU inputs from routing. - Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. * Abundant high-speed buffered and non-buffered routing resources provide 2x average speed improvements over previous architectures. * Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. * SLIC provides eight 3-state buffers, up to a 10-bit decoder, and PALTM-like AND-OR-Invert (AOI) in each programmable logic cell. * New 200 MHz embedded quad-port RAM blocks, 2 read ports, 2 write ports, and 2 sets of byte lane enables. Each embedded RAM block can be configured as: - 1--512 x 18 (quad-port, two read/two write) with optional built in arbitration.
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Lattice Semiconductor
- - - - - - - - -
ORCA ORSPI4 Data Sheet
1--256 x 36 (dual-port, one read/one write). 1--1K x 9 (dual-port, one read/one write). 2--512 x 9 (dual-port, one read/one write for each). 2 RAMS with an arbitrary number of words whose sum is 512 (or less) x 18 (dual-port, one read/one write). Supports joining of RAM blocks. Two 16 x 8-bit content addressable memory (CAM) support. FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9. Constant multiply (8 x 16 or 16 x 8). Dual variable multiply (8 x 8).
* Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are builtin system registers that act as the control and status center for the device. * Built-in testability: - Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG). - Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. - TS_ALL testability function to 3-state all I/O pins. - New temperature-sensing diode. * Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to 420 MHz. Multiplication of the input frequency up to 64x and division of the input frequency down to 1/64x possible. * New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers.
Programmable Logic System Features
* PCI local bus compliant for FPGA I/Os. * Improved PowerPC (R) 860 and PowerPC II high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space provided. * New embedded AMBA TM specification 2.0 AHB system bus (ARM (R) processor) facilitates communication among the microprocessor interface, configuration logic, Embedded Block RAM, FPGA logic, and embedded standard cell blocks. * Variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. * Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. * New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for OR4E04). * New local clock routing structures allow creation of localized clock trees. * Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved setup/hold and clock to out performance. * New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest highspeed memory interfaces. * New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal logic. * Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) levels 1, 2, and 3; as well as POS-PHY3.
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ORCA ORSPI4 Data Sheet
PLC Logic Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional Flip-Flop that may be used independently or with arithmetic functions. The PFU is organized in a twin-quad fashion; two sets of four LUTs and FFs that can be controlled independently. Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidirectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for realworld system performance. Programmable I/O The Series 4 PIO addresses the demand for the flexibility to select I/Os that meet system interface requirements. I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features which allow the user the flexibility to select new I/O types that support High-Speed Interfaces. Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset, and global set/reset. On the input side, each PIO contains a programmable latch/Flip-Flop, which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer with a PFU. On the output side of each PIO, an output from the PLC array can be routed to each output Flip-Flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3state signal can be registered or nonregistered. The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These modes are supported through shift register logic, which divides down incoming data rates, or multiplies up outgoing data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and out of the I/O buffers on both edges of the clock. The new programmable I/O cell allows designers to select I/Os which meet many new communication standards permitting the device to hook up directly without any external interface translation. They support traditional FPGA standards as well as high-speed, single-ended, and differential-pair signaling. Based on a programmable, bank-oriented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output levels. Routing The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses with related control signals. Both local and global signals utilize high-speed buffered and non-buffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance.
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ORCA ORSPI4 Data Sheet
Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can be sourced from any I/O pin, PLLs, or the PLC logic. The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins.
System-Level Features
The Series 4 also provides system-level functionality by means of its microprocessor interface, Embedded System Bus, quad-port Embedded Block RAMs, universal programmable Phase-Locked Loops, and the addition of highly tuned networking specific Phase-Locked Loops. These functional blocks allow for easy, glueless system interfacing and the capability to adjust to varying conditions in today's high-speed networking systems. MicroProcessor Interface The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-bit, 16-bit, and 32-bit interfaces with optional parity to the Motorola(R) PowerPC 860 bus, it can be used for configuration and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4 Embedded System Bus at 66 MHz performance. A system-level microprocessor interface to the FPGA user-defined logic following configuration, through the system bus, including access to the Embedded Block RAM and general user-logic, is provided by the MPI. The MPI supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes). System Bus An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, configuration logic, FPGA control, and status registers, Embedded Block RAMs, as well as user logic. Utilizing the AMBA specification Rev 2.0 AHB protocol, the Embedded System Bus offers arbiter, decoder, master, and slave elements. Master and slave elements are also available for the user-logic and a slave interface is used for control and status of the embedded backplane transceiver portion of the ORSPI4. The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset functions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the microprocessor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from routing, or from the port clock (for JTAG configuration modes). Phase-Locked Loops The ORSPI4 provides 4 programmable PLLs accessible through clock routing in the FPGA array. There are two standard programmable PLLs (PPLL) and 2 high-speed programmable PLLs (HPPLL) available in the ORSPI4. The two PPLLs are capable of manipulating and conditioning clock outputs from 15 MHz to 200 MHz. The two HPPLLs are capable of manipulating and conditioning clock outputs from 60 MHz to 420 MHz. Programmable PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Frequencies can be adjusted from 1/8x to 8x, the input clock frequency. Each programmable PLL provides two outputs that have different multiplication factors but can have the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic input buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences.
FPGA Configuration
The FPGA functionality is determined by internal configuration RAM. The FPGAs internal initialization/configuration circuitry loads the configuration data at power-up or under system control. The configuration data can reside exter-
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
nally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for configuring FPGAs. The RAM is loaded by using one of several configuration modes. Supporting the traditional master/slave serial, master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its microprocessor interface and Embedded System Bus to perform both programming and readback. Daisy chaining of multiple devices and partial reconfiguration are also permitted. Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory, as well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE 1149.2) port is also available, meeting In-System Programming (ISP) standards (IEEE 1532 Draft).
FPSC Configuration
Configuration of the ORSPI4 occurs in two stages: FPGA bit-stream configuration and embedded core setup. Prior to becoming operational, the FPGA goes through a sequence of states, including power-up, initialization, configuration, start-up, and operation. The FPGA logic is configured by standard FPGA bit-stream configuration means as discussed in the ORCA Series 4 FPGA data sheet. After the FPGA configuration is complete, the options for the embedded core are set based on the contents of registers that are accessed through the FPGA system bus. The system bus itself can be driven by an external PowerPC compliant microprocessor via the MPI block or via a user master interface in FPGA logic. A simple IP block that drives the system by using the user register interface and very little FPGA logic is available in the MPI/System Bus Technical Note (TN-1017). This IP block sets up the embedded core via a state machine and allows the ORSPI4 to work in an independent system without an external microprocessor interface.
ORSPI4 Package Options
The ORSPI4 FPSC is available in two package options: a 1036 ftSBGA and a 1156 fpBGA. The 1036 pin package provides an OR4E06 FPGA array (16,192 LEs, 148 Kbits of Embedded Block RAM), 498 FPGA user I/Os, two SPI4 interfaces (or one SPI4 interface and a quad high-speed SERDES interface), and a high-speed QDRII SRAM Controller. The 1156 pin package provides an OR4E06 FPGA array (16,192 LEs, 148 Kbits of Embedded Block RAM), 356 FPGA user I/Os, two SPI4 interfaces (SERDES interface not available on this package), and a highspeed QDRII SRAM Controller.
Additional Information
Contact your local Lattice representative for additional information regarding the ORCA Series 4 FPGA devices, or visit our website at: http://www.latticesemi.com/orca
Links to Specs and Standards
Optical Internetworking Forum - OIF-SPI4-02.0 - www.oiforum.com Fibre Channel Physical and Signaling Interface - FC-PH ANSI X3.230-1994 - www.t11.org 10 Gigabit Ethernet - IEEE P802.3ae - www.ieee.org 18Mb QDR-II SRAM 2-word burst - MT54W512H36B - www.cypress.com/products/micron/micron.cfm 18Mb QDR-II SRAM 4-word burst - MT54W512H36B - www.cypress.com/products/micron/micron.cfm 36Mb QDR-II SRAM 2-word burst - KTR323682M - www.samsung.com/Products/Semiconductor/SRAM/index.htm 36Mb QDR-II SRAM 4-word burst - KTR323684M - www.samsung.com/Products/Semiconductor/SRAM/index.htm
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ORCA ORSPI4 Data Sheet
ORSPI4 SPI4 Data Formats
The data format across the SPI4 interface follows the OIF SPI4 convention where the lowest byte number occupies the highest bit positions within the 16-bit word as shown in Figure 5. On payload transfers that do not end on an even byte boundary, the unused byte (after the last valid byte) on bit positions 7 through 0 is set to all zeroes as shown in Figure 5.
Figure 5. SPI4 Byte and Bit Ordering
15 Byte 0 7 Byte 2 Byte 4 15 7 Byte 0 Byte 2 Byte 4 Byte 1 Byte 3 x (set to zeros) Byte 1 Byte 3 x (set to zeros) 0 0
TDAT
RDAT
At the FPGA-embedded core RX and TX interface, the same SPI4 convention is followed wherein the lowest byte number occupies the highest bit positions within a word. This is the same in all operating modes - 32-bit, 64-bit and 128-bit. Byte enables for all data except EOP should be "1". During an EOP, the last valid byte enable within a 32-bit, 64-bit or 128-bit word indicates the last byte for the packet. Figure 6 shows EOP signal being asserted during Word 3. In Figure 6, the last valid byte enable within "1110" in Word 3 indicates the EOP. The valid byte enables during an EOP are "1111", "1110", "1100" and "1000". If the packet was errored, the ERR signal is asserted and will remain asserted until EOP as shown in Figure 6
Figure 6. Example of EOP Indication in 32-Bit Mode
Word 0 0123 Byte BE0 111 Bit SPI[A,B]_TX32_EOP_j SPI[A,B]_RX32_EOP_j SPI[A,B]_TX32_ERR_j SPI[A,B]_RX32_ERR_j Clock 1 Clock 2 Clock 3 Clock 4 1 BE1 1111 BE2 111 1 BE3 11 10 Word 1 0123 Word 2 0123 Word 3 0123
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
The bit ordering in the data format in the 32-bit aggregation mode is shown in Figure 7. In 32-bit mode, data transfers are done in 4-word bursts with the exception of an EOP. As shown in the figure, SOP is always aligned to the most significant 32-bit word, Word 0 of a 4-word burst. The first byte of a packet is always Word 0. The SOP indicator is high during Word 0. EOP can be any byte within the 32-bit word. The last valid byte enable within a 32-bit word indicates the end of packet. The EOP signal can be high during Word 0, Word 1, Word 2 or Word 3. It should be used in conjunction with the byte enables to determine the last byte in that data transfer. If data transfers do not end on Word 3, then the burst is terminated and Word 0 of the next burst is sent to the user. For example, if EOP occurs during Word 2, Word 3 will be discarded and Word 0 of the next word will be sent to the user.
Figure 7. Byte and Bit Ordering in 32-Bit Operating Mode
SPI[A,B]_TX32_DATA_j[31:0] or SPI[A,B]_RX32_DATA_j[31:0]
FPGA
127
DPRAM
95 63 31 0
W0 W1 W2 W3
31 23 15 7 0 31 23 15 7 0 31 23 15 7 0 31 23 15 7 0 Byte 0 Byte 1Byte 2 Byte 3 Byte 0 Byte 1 Byte 2 Byte 3 Byte 0 Byte 1Byte 2 Byte 3 Byte 0 Byte 1 Byte 2 Byte 3
Word 0 SPI[A,B]_RX32_SOP_j SPI[A,B]_RX32_SOP_j
Word 1
Word 2
Word 3
Clock 1
Clock 2 Time
Clock 3
Clock 4 Byte 0 is the SOP
The bit ordering in the data format in the 64-bit aggregation mode is shown in Figure 8. In 64-bit mode, data transfers are done in 2-word bursts with the exception of an EOP. As shown in the figure, SOP is always aligned to the most significant 64-bit Word 0 of a 2-word burst. The first byte of a packet is always Word 0. The SOP indicator is high during word Word 0.
Figure 8. Byte and Bit Ordering in 64-Bit Mode
SPI[A,B]_TX64_DATA_j[63:0] SPI[A,B]_RX64_DATA_j[63:0] or
63 55 47 39 32 31 23 15 7 0 63 55 47 39 32 31 23
FPGA
15 7 0 127
DPRAM
95 63
31 0
Byte 0 Byte 1Byte 2 Byte 3 Byte 4Byte 5Byte 6 Byte 7
Byte 0 Byte 1Byte 2 Byte 3 Byte4 Byte 5Byte 6 Byte 7
Word 0
Word 1
Word 0 SPI[A,B]_TX64_SOP_j SPI[A,B]_RX64_SOP_j
Word 1
Clock 1 Time
Clock 2
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
The bit ordering in the data format in the 128-bit aggregation mode is shown in Figure 9. The first byte of a packet is always byte 0 of the 128-bit word. As shown in the figure, SOP is always aligned to the most significant 64-bit Word 0 of a 2-word burst. SOP is always aligned to byte 0 of the 128-bit word.
Figure 9. Byte and Bit Ordering in 128-Bit Mode
SPI[A,B]_TX128_DATA[127:0] or SPI[A,B]_RX128_DATA[127:0]
127 119 111 103 96 95 87 79 71 64 63 55 47 39 3231 23 15
FPGA
127
DPRAM
95 63 31 0
7
0
Byte 0 Byte 1 Byte 2 Byte 3
Byte 4 Byte 5 Byte 6 Byte 7
Byte 8 Byte 9 Byte 10 Byte 11 Byte12 Byte 13 Byte 14 Byte 15
Word 0
Word 0 SPI[A,B]_TX128_SOP SPI[A,B]_RX128_SOP
Clock 1 Time
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
SPI4 Transmit Path Functional Description
This section describes the transmit section of the SPI4 interface. The ORSPI4 device contains two identical, yet independent Transmit SPI4 compliant interfaces within the FPSC. The description provided within this section is applicable to both Transmit SPI4 interfaces. The Transmit SPI4 interface supports the following features: * Independent TX interface that is not tied to associated Receive SPI4 interface * 10 Gbit/s data throughput * 4 dual-port memories used to provide 256 Bytes of buffering for up to 32 ports. If support for more than 32 ports is required, the dual-port memories can be used, or they can be used for clock crossing purposes while data is buffered with external memory. * Simple FIFO-like interface from FPGA to SPI4 TX embedded core block. * Calendar Control Logic, including the Transmit Calendar, Shadow Calendar and support for up to 256 ports (the maximum allowable number of SPI4 ports). * Mixed data width aggregation modes at the user Transmit interface. 32, 64, and 128-bit modes are supported. * Programmable calendar table, supporting all calendar configuration parameters as specified in the SPI4 standard. * Feedback to FPGA of currently serviced SPI4 port. The Transmit SPI4 logic enables users to write port data from a variety of interfaces and associated clock domains using Dual Port RAMs (DPRAM) for temporary storage and clock domain crossing. Data is written into the DPRAM banks from the FPGA and read according to a pre-configured transmit calendar sequence. Data is formatted into the SPI4 format and transmitted to the physical links as LVDS signals, as specified by OIF-SPI4-02.0. In addition to the transmit data path, out-of-band status information is received on the Transmit Status lines. This information is used, along with preconfigured Calendar sequence information, to schedule the servicing of SPI4 port for data transmission. The status information is also passed back to the FPGA logic. There are also several other features incorporated into the embedded core such as parallel loopback and SPI4 loopback to assist in debugging and statistic gathering. The major blocks associated with the ORSPI4 transmitter are: * Four Transmit DPRAM Banks * Address Map and Arbiter (AMA) * Transmit Calendar Control Logic - Port Write Sequencer Logic (PWS) * SPI4 Logic - Data - SPI4 Transmit Data Logic (TDP) - SPI4 Transmit I/O Interface (TDO) * SPI4 Transmit Status Logic (TSP) - SPI4 Transmit Status Interface (TSI) - SPI4 Transmit Status Protocol (TSP) These blocks will be described in detail in the following sections. The ORSPI4 Transmit functional block diagram is shown in Figure 10. .
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Lattice Semiconductor
Figure 10. ORSPI4 Transmit Functional Block Diagram
k = TX32, TX64 or TX128 j = 0, 1, 2 or 3
SPI[A,B]_k_DATA_j, BEj SPI[A,B]_k_SOPj, ERRj
ORCA ORSPI4 Data Sheet
FPGA Interface
SPI[A,B]_k_ADDRj SPI[A,B]_k_PORT_j SPI[A,B]_k_WE_j SPI[A,B]_k_WD_CNT_RST_j SPI[A,B]_k_LINK_DIS_j SPI[A,B]_k_FIFO_FULL_j SPI[A,B]_k_CLK_j
16
[A,B]TDAT [A,B]TCTL [A,B]TDCLK
TX DPRAM
Address Map & Arbiter
TDP TDP
TDO
SPI[A,B]_k_PORT_ID AMA_ID BURST_VAL
SPI[A,B]_k_PORT_ID SPI[A,B]_k_STAT SPI[A,B]_k_BURST_VAL
8
PORT_ID
2
TLSTAT TLCLK TSI
2
[A,B]TSTAT [A,B]TSCLK
TX Calendar Control Logic
PORT_STAT TSP
4
ORSPI4 Transmit Functional Block Overview
The user can write transmit data and associated control signals to the TX DPRAM bank using either multiple 32- or 64-bit interfaces, or a single aggregated 128-bit interface. The data bus interface is software configurable. The TX DPRAM block is made up of 4 configurable DPRAMs, used for transmit data buffering and clock domain crossing. The DPRAMs can be configured via software to support up to 8 virtual partitions each, providing a maximum of 32 virtual FIFOs, each being 256 Bytes deep. Data is read from the DPRAMs according to the configured Transmit Calendar within the TX Calendar Control Logic. The control logic provides both the virtual partition address and BURST_VAL to the Address Map & Arbiter (AMA) block. The AMA services the requested partition and can optionally provide idle data if the partition is empty when serviced. The TDP block accepts transmit data and control signals from the AMA and formats the data according to the SPI4 transmit data protocol. The transmit data is then serialized within the TDO block. Data is transmitted across the SPI4 interface on a 16-bit LVDS pair bus (TDAT) which is source synchronous to the LVDS pair clock (TDCLK). The LVDS control signal pair (TCTL) is used to identify when the content of the SPI4 bus is control versus user data. The interface is an OIF-SPI-4 02.0 compliant interface that supports data rates in the range of 622-900 Mbps. Additionally, lower speed data in the range of 100200 Mbps is also supported. To accommodate dynamic timing the TDP will insert training patterns as configured.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Far-end status is received by the TSI block and sent to the TSP block for buffering. The interface supports quarterrate status from either LVDS or TTL inputs. The TSP block provides both the port identification and current status to the TX Calendar Control Logic, where internal tables are updated accordingly to provide proper port servicing.
ORSPI4 Transmit FPGA/Embedded Core Interface Description
The FPGA I/O interface to the ORSPI4 logic supports several interface features and varying interface characteristics, depending upon the configured mode of operation. The modes are referred to as 'aggregation modes' due to the nature of the aggregation of data busses for the different modes of operation. There are three data aggregation modes supported by the Transmit Core: * 32-bit mode: Each of the 4 DPRAMs can be configured to use a 32-bit user data interface plus associated control signals across the FPGA interface. This interface is useful when interfacing the SPI4 data pipe to one or more sub-rate channels. This mode provides up to 4 independent 32-bit interfaces. In this mode, the interfaces do not need to be synchronous with each other. * 64-bit mode: DPRAM pairs {[0:1], [2:3]} are configured to serve as 64-bit user data interfaces, plus associated control signals. Note that 32-bit and 64-bit modes can be combined to provide up to 3 independent interfaces. * 128-bit mode: All four DPRAM banks are aggregated into a single FIFO with a 128-bit user-data interface from the FPGA. * To maintain compliance with the SPI-4.2 interface protocol, the user is required to burst a minimum of 16 data bytes per write period. This is required for all modes of aggregation. For 32-bit mode, four writes are required, for 64-bit mode, two writes are required. For 128-bit mode, a single write access will provide 16 bytes of data. Several other features are: * Auto-increment of the DPRAM write address pointer when an EOP is detected. * Prohibit data writes if no associated byte-enable (BE) bits are asserted within an entire 128-bit line, optimizing the FIFO memory locations by not wasting memory. * The ability for the user to disable one or more of the interface links using the SPI[A,B]_k_LINK_DIS_j signals. This causes the AMA logic to cease polling from a DPRAM. All ports associated with a disabled DPRAM will remain unserviced until the control signal is deasserted. * The ability for the user to reset a port's write pointer with the SPI[A,B]_k_WD_CNT_RST_j signal. This can be used to customize data applications or as a diagnostic test function. * The ability for the user to individually poll for DPRAM FIFO fill status. Normal FIFO status is provided whenever the user attempts to write data to the DPRAMs. If an address is provided to the FIFO without a write enable, FIFO status is still provided. This feature is useful when the application requires knowing the status of individual virtual FIFOs but is not prepared to write data to it. Table 2 lists the I/Os for the Transmit SPI4A core only. The interface signals for core B are identical with the names modified appropriately. Table 3 and Table 4 list the I/O for the Transmit SPI4 core for 64-bit and 128-bit aggregation modes respectively.
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Table 2. SPIA Core Transmit FPGA Interface in 32-Bit Mode
DPRAM FPGA Interface I/Os SPIA_TX32_ADDR_0[2:0] Direction From/To
ORCA ORSPI4 Data Sheet
Description
FPGA Core Virtual FIFO write address. Each DPRAM can be divided up to a maximum of eight partitions. More than one port can be configured to share a virtual FIFO partition. FPGA Core User Write data. Four writes are required in order to complete an entire 128bit line. All writes must occur in four write bursts, unless an EOP occurs. FPGA Core Byte enables indicating which bytes within the 32-bit word are valid. Bit[3]-Byte enable for SPIA_TX32_DATA_0[31:24] Bit[2]-Byte enable for SPIA_TX32_DATA_0[23:16] Bit[1]-Byte enable for SPIA_TX32_DATA_0[15:8] Bit[0]-Byte enable for SPIA_TX32_DATA_0[7:0] If no BE bits are asserted for a particular location within the DPRAM, port data will be dropped and no write to the DPRAM will occur. According to the SPI-4.2 specification, the BE bits must be asserted for all but the last transfer, where an End of Packet or Error may occur. The valid combinations of BE are as follows: BE[3:0] = 1111--indicates all four bytes contain valid user data BE[3:0] = 1110--indicates three bytes are valid. EOP occurs in third Byte. BE[3:0] = 1100--indicates two bytes are valid. EOP occurs in second Byte. BE[3:0] = 1000--indicates one byte is valid. EOP occurs in first Byte. FPGA Core Start of Packet indicator. A '1' indicates the start of packet for a particular port. When operating in either 32- or 64-bit mode, the SOP indicator must be asserted coincident with the first write per address line within the FIFO partition. FPGA Core End of Packet indicator. A '1' indicates the end of packet for a particular port. The EOP may be asserted on any write per address line within the FIFO partition. When an EOP is detected by the DPRAM Write Pointer Logic, the address pointer will be automatically incremented to the next location within the FIFO partition range. FPGA Core Packet error indication. A '1' indicates an error has occurred for the current packet being transmitted. The ERR signal must be asserted coincident with the EOP signal. FPGA Core Write Enable. A logic '1' causes data on the SPIA_TX32_DATA_0[31:0] bus to be captured for a write to the DPRAM. FPGA Core SPI4 port indicator, used to associate the current transmit data with a particular port number.
SPIA_TX32_DATA_0[31:0] SPIA_TX32_BE_0[3:0]
SPIA_TX32_SOP_0
SPIA_TX32_EOP_0
0
SPIA_TX32_ERR_0
SPIA_TX32_WE_0 SPIA_TX32_PORT_0[7:0]
SPIA_TX32_WD_CNT_RST_ FPGA Core Line Write Termination indicator. This signal causes the FIFO write address 0 pointer within the embedded core to increment to the next address location for the addressed partition. This signal can be used for custom applications as well as for diagnostic test functions. SPIA_TX32_LINK_DIS_0 FPGA Core Link disable control signal. When asserted to a logic '1', the AMA will cease polling from a DPRAM. All ports associated with a disabled DPRAM will remain unserviced until the control signal is deasserted. The AMA will send IDLE data across the SPI4 link. If the application continues to write data to that port FIFO, it will eventually fill and provide proper FIFO fill status to the application. FPGA Core Transmit write reference clock. The clocks across the different transmit interfaces are independent from each other, and are not required to be synchronous to each other. Core FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX32_ADDR_0[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the configured fill level within the partition.
SPIA_TX32_CLK_0
SPIA_TX32_FIFO_FULL_0
Note: For SPIB replace A with B
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Lattice Semiconductor
Table 2. SPIA Core Transmit FPGA Interface in 32-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_TX32_ADDR_1[2:0] Direction From/To
ORCA ORSPI4 Data Sheet
Description
FPGA Core Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum of eight partitions. More than one port can be configured to share a virtual FIFO partition. FPGA Core User Write data. Four writes are required in order to complete an entire 128-bit line. All writes must occur in four write bursts, unless an EOP occurs. FPGA Core Byte enables indicating which bytes within the 32-bit word are valid. Bit[3]-Byte enable for SPIA_TX32_DATA_0[31:24] Bit[2]-Byte enable for SPIA_TX32_DATA_0[23:16] Bit[1]-Byte enable for SPIA_TX32_DATA_0[15:8] Bit[0]-Byte enable for SPIA_TX32_DATA_0[7:0] If no BE bits are asserted for a particular location within the DPRAM, port data will be dropped and no write to the DPRAM will occur. According to the SPI-4.2 specification, the BE bits must be asserted for all but the last transfer, where an End of Packet or Error may occur. The valid combinations of BE are as follows: BE[3:0] = 1111--indicates all four bytes contain valid user data BE[3:0] = 1110--indicates three bytes are valid. EOP occurs in third Byte. BE[3:0] = 1100--indicates two bytes are valid. EOP occurs in second Byte. BE[3:0] = 1000--indicates one byte is valid. EOP occurs in first Byte. FPGA Core Start of Packet indicator. A '1' indicates the start of packet for a particular port. When operating in either 32- or 64-bit mode, the SOP indicator must be asserted coincident with the first write per address line within the FIFO partition. FPGA Core End of Packet indicator. A '1' indicates the end of packet for a particular port. The EOP may be asserted on any write per address line within the FIFO partition. When an EOP is detected by the DPRAM Write Pointer Logic, the address pointer will be automatically incremented to the next location within the FIFO partition range. FPGA Core Packet error indication. A '1' indicates an error has occurred for the current packet being transmitted. The ERR signal must be asserted coincident with the EOP signal. FPGA Core Write Enable. A logic '1' causes data on the SPIA_TX32_DATA_1[31:0] bus to be captured for a write to the DPRAM. FPGA Core SPI4 port indicator, used to associate the current transmit data with a particular port number.
SPIA_TX32_DATA_1[31:0]
SPIA_TX32_BE_1[3:0]
SPIA_TX32_SOP_1
SPIA_TX32_EOP_1
1
SPIA_TX32_ERR_1
SPIA_TX32_WE_1 SPIA_TX32_PORT_1[7:0]
SPIA_TX32_WD_CNT_RST_ FPGA Core Line Write Termination indicator. This signal causes the FIFO write address 1 pointer within the embedded core to increment to the next address location for the addressed partition. This signal can be used for custom applications as well as for diagnostic test functions. SPIA_TX32_LINK_DIS_1 FPGA Core Link disable control signal. When asserted to a logic '1', the AMA will cease polling from a DPRAM. All ports associated with a disabled DPRAM will remain unserviced until the control signal is deasserted. The AMA will send IDLE data across the SPI4 link. If the application continues to write data to that port FIFO, it will eventually fill and provide proper FIFO fill status to the application. FPGA Core Transmit write reference clock. The clocks across the different transmit interfaces are independent from each other, and are not required to be synchronous to each other. Core FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX32_ADDR_1[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the configured fill level within the partition.
SPIA_TX32_CLK_1
SPIA_TX32_FIFO_FULL_1
Note: For SPIB replace A with B
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Lattice Semiconductor
Table 2. SPIA Core Transmit FPGA Interface in 32-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_TX32_ADDR_2[2:0] Direction From/To
ORCA ORSPI4 Data Sheet
Description
FPGA Core Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum of eight partitions. More than one port can be configured to share a virtual FIFO partition. FPGA Core User Write data. Four writes are required in order to complete an entire 128-bit line. All writes must occur in four write bursts, unless an EOP occurs. FPGA Core Byte enables indicating which bytes within the 32-bit word are valid. Bit[3]-Byte enable for SPIA_TX32_DATA_0[31:24] Bit[2]-Byte enable for SPIA_TX32_DATA_0[23:16] Bit[1]-Byte enable for SPIA_TX32_DATA_0[15:8] Bit[0]-Byte enable for SPIA_TX32_DATA_0[7:0] If no BE bits are asserted for a particular location within the DPRAM, port data will be dropped and no write to the DPRAM will occur. According to the SPI-4.2 specification, the BE bits must be asserted for all but the last transfer, where an End of Packet or Error may occur. The valid combinations of BE are as follows: BE[3:0] = 1111--indicates all four bytes contain valid user data. If an EOP is present, it resides within the fourth byte. BE[3:0] = 1110--indicates three bytes are valid. EOP occurs in third Byte. BE[3:0] = 1100--indicates two bytes are valid. EOP occurs in second Byte. BE[3:0] = 1000--indicates one byte is valid. EOP occurs in first Byte. FPGA Core Start of Packet indicator. A '1' indicates the start of packet for a particular port. When operating in either 32- or 64-bit mode, the SOP indicator must be asserted coincident with the first write per address line within the FIFO partition. FPGA Core End of Packet indicator. A '1' indicates the end of packet for a particular port. The EOP may be asserted on any write per address line within the FIFO partition. When an EOP is detected by the DPRAM Write Pointer Logic, the address pointer will be automatically incremented to the next location within the FIFO partition range. FPGA Core Packet error indication. A '1' indicates an error has occurred for the current packet being transmitted. The ERR signal must be asserted coincident with the EOP signal. FPGA Core Write Enable. A logic '1' causes data on the SPIA_TX32_DATA_2[31:0] bus to be captured for a write to the DPRAM. FPGA Core SPI4 port indicator, used to associate the current transmit data with a particular port number.
SPIA_TX32_DATA_2[31:0]
SPIA_TX32_BE_2[3:0]
SPIA_TX32_SOP_2
SPIA_TX32_EOP_2 2
SPIA_TX32_ERR_2
SPIA_TX32_WE_2 SPIA_TX32_PORT_2[7:0]
SPIA_TX32_WD_CNT_RST_ FPGA Core Line Write Termination indicator. This signal causes the FIFO write address 2 pointer within the embedded core to increment to the next address location for the addressed partition. This signal can be used for custom applications as well as for diagnostic test functions. SPIA_TX32_LINK_DIS_2 FPGA Core Link disable control signal. When asserted to a logic '1', the AMA will cease polling from a DPRAM. All ports associated with a disabled DPRAM will remain unserviced until the control signal is deasserted. The AMA will send IDLE data across the SPI4 link. If the application continues to write data to that port FIFO, it will eventually fill and provide proper FIFO fill status to the application. FPGA Core Transmit write reference clock. The clocks across the different transmit interfaces are independent from each other, and are not required to be synchronous to each other. Core FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX32_ADDR_3[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the configured fill level within the partition.
SPIA_TX32_CLK_2
SPIA_TX32_FIFO_FULL_2
Note: For SPIB replace A with B
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Table 2. SPIA Core Transmit FPGA Interface in 32-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_TX32_ADDR_3[2:0] Direction From/To
ORCA ORSPI4 Data Sheet
Description
FPGA Core Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum of eight partitions. More than one port can be configured to share a virtual FIFO partition. FPGA Core User Write data. Four writes are required in order to complete an entire 128-bit line. All writes must occur in four write bursts, unless an EOP occurs. FPGA Core Byte enables indicating which bytes within the 32-bit word are valid. Bit[3]-Byte enable for SPIA_TX32_DATA_0[31:24] Bit[2]-Byte enable for SPIA_TX32_DATA_0[23:16] Bit[1]-Byte enable for SPIA_TX32_DATA_0[15:8] Bit[0]-Byte enable for SPIA_TX32_DATA_0[7:0] If no BE bits are asserted for a particular location within the DPRAM, port data will be dropped and no write to the DPRAM will occur. According to the SPI-4.2 specification, the BE bits must be asserted for all but the last transfer, where an End of Packet or Error may occur. The valid combinations of BE are as follows: BE[3:0] = 1111--indicates all four bytes contain valid user data. If an EOP is present, it resides within the fourth byte. BE[3:0] = 1110--indicates three bytes are valid. EOP occurs in third Byte. BE[3:0] = 1100--indicates two bytes are valid. EOP occurs in second Byte. BE[3:0] = 1000--indicates one byte is valid. EOP occurs in first Byte. FPGA Core Start of Packet indicator. A '1' indicates the start of packet for a particular port. When operating in either 32- or 64-bit mode, the SOP indicator must be asserted coincident with the first write per address line within the FIFO partition. FPGA Core End of Packet indicator. A '1' indicates the end of packet for a particular port. The EOP may be asserted on any write per address line within the FIFO partition. When an EOP is detected by the DPRAM Write Pointer Logic, the address pointer will be automatically incremented to the next location within the FIFO partition range. FPGA Core Packet error indication. A '1' indicates an error has occurred for the current packet being transmitted. The ERR signal must be asserted coincident with the EOP signal. FPGA Core Write Enable. A logic '1' causes data on the SPIA_TX32_DATA_3[31:0] bus to be captured for a write to the DPRAM. FPGA Core SPI4 port indicator, used to associate the current transmit data with a particular port number.
SPIA_TX32_DATA_3[31:0]
SPIA_TX32_BE_3[3:0]
SPIA_TX32_SOP_3
SPIA_TX32_EOP_3 3
SPIA_TX32_ERR_3
SPIA_TX32_WE_3 SPIA_TX32_PORT_3[7:0]
SPIA_TX32_WD_CNT_RST_ FPGA Core Line Write Termination indicator. This signal causes the FIFO write address 3 pointer within the embedded core to increment to the next address location for the addressed partition. This signal can be used for custom applications as well as for diagnostic test functions. SPIA_TX32_LINK_DIS_3 FPGA Core Link disable control signal. When asserted to a logic '1', the AMA will cease polling from a DPRAM. All ports associated with a disabled DPRAM will remain unserviced until the control signal is deasserted. The AMA will send IDLE data across the SPI4 link. If the application continues to write data to that port FIFO, it will eventually fill and provide proper FIFO fill status to the application. Transmit write reference clock. The clocks across the different transmit FPGA Core interfaces are independent from each other, and are not required to be synchronous to each other. Core FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX32_ADDR_3[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the configured fill level within the partition.
SPIA_TX32_CLK_3
SPIA_TX32_FIFO_FULL_3
Note: For SPIB replace A with B
33
Lattice Semiconductor
Table 2. SPIA Core Transmit FPGA Interface in 32-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_TX32_PORT_ID[7:0] Direction From/To
ORCA ORSPI4 Data Sheet
Description
Port number of the currently serviced SPI4 data port. The value can either Core FPGA be the actual SPI4 value or a programmed user value. Further details are provided in the TX Calendar Control Logic description. Status of the SPI4 port currently being serviced. These signals can be Core FPGA used in conjunction with the SPIA_TX32_PORT_ID signal to police transmit traffic congestion for a particular SPI4 port. Indicates the number of SPI4 cycles for which the currently active port will Core FPGA be serviced. Each cycle indicates an attempt to read 128 bits of data from the respective FIFO partition. Core FPGA Transmit reference clock. This clock signal is 1/4th the SPI4 clock. This signal can be used to synchronize FPGA application logic to the FPSC logic.
SPIA_TX32_STAT[1:0]
SPIA_TX32_BURST_VAL[3:0] Status I/Os ATREFCLK_F SPIA_TREFCLK_X8
Quarter-rate Transmit reference clock. This FPGA-sourced clock reference must be 2x the desired Transmit SPI4 line clock rate. When not operating FPGA Core the Transmit SPI4 core in Quarter-rate mode, this signal should be tied off. Ex: For a 100 MHz Transmit SPI4 line clock, SPIA_TREFCLK_X8 from the FPGA must be 200 MHz. FPGA Core `0' - Incoming ATSCLK is assumed to be edge-aligned with the data and centered to the data eye within the chip. `1' - Incoming ATSCLK is assumed to be skewed with respect to the data off-chip.
SPI_SATM_A Misc. I/Os
Note: For SPIB replace A with B
34
Lattice Semiconductor
Table 3. SPIA Core Transmit FPGA Interface in 64-Bit Mode
DPRAM FPGA Interface I/Os SPIA_TX64_ADDR_0[2:0] Direction From/To
ORCA ORSPI4 Data Sheet
Description
FPGA Core Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum of eight partitions. When operating in 64-bit mode, each partition will be 2x the depth of the corresponding partition in 32-bit mode. More than one port can be configured to share a virtual FIFO partition. FPGA Core User Write data. Two writes are required in order to complete an entire 128bit line. All writes must occur in two write bursts, unless an EOP occurs. FPGA Core Byte enables indicating which bytes within the 64-bit word are valid. Bit[7]-Byte enable for SPIA_TX64_DATA_0[63:56] Bit[6]-Byte enable for SPIA_TX64_DATA_0[55:48] Bit[5]-Byte enable for SPIA_TX64_DATA_0[47:40] Bit[4]-Byte enable for SPIA_TX64_DATA_0[39:32] Bit[3]-Byte enable for SPIA_TX64_DATA_0[31:24] Bit[2]-Byte enable for SPIA_TX64_DATA_0[23:16] Bit[1]-Byte enable for SPIA_TX64_DATA_0[15:8] Bit[0]-Byte enable for SPIA_TX64_DATA_0[7:0] If no BE bits are asserted for a particular location within the DPRAM, data will be dropped and no write to the DPRAM will occur. According to the SPI-4.2 specification, the BE bits must be asserted for all but the last transfer, where an End of Packet or Error may occur. The valid combinations of BE are as follows: BE[7:0] = 11111111--indicates all eight bytes contain valid user data. If an EOP is present, it resides within the eighth byte. BE[7:0] = 11111110--indicates seven bytes are valid. EOP occurs in seventh Byte. BE[7:0] = 11111100--indicates six bytes are valid. EOP occurs in sixth Byte. BE[7:0] = 11111000--indicates five byte is valid. EOP occurs in fifth Byte. BE[7:0] = 11110000--indicates four bytes are valid. EOP occurs in fourth Byte. BE[7:0] = 11100000--indicates three bytes are valid. EOP occurs in third Byte. BE[7:0] = 11000000--indicates two bytes are valid. EOP occurs in second Byte. BE[7:0] = 10000000--indicates one byte is valid. EOP occurs in first Byte. FPGA Core Start of Packet indicator. A '1' indicates the start of packet for a particular port. When operating in 64-bit mode, the SOP indicator must be asserted coincident with the first write per address line within the FIFO partition. FPGA Core End of Packet indicator. A '1' indicates the end of packet for a particular port. The EOP may be asserted on either write per address line within the FIFO partition. When an EOP is detected by the DPRAM Write Pointer Logic, the address pointer will be automatically incremented to the next location within the FIFO partition range. FPGA Core Packet error indication. A '1' indicates an error has occurred for the current packet being transmitted. The ERR signal must be asserted coincident with the EOP signal. FPGA Core Write Enable. A logic '1' causes data on the SPIA_TX64_DATA_0[63:0] bus to be captured for a write to the DPRAM. FPGA Core SPI4 port indicator, used to associate the current transmit data with a particular port number.
SPIA_TX64_DATA_0[63:0] SPIA_TX64_BE_0[7:0]
0
SPIA_TX64_SOP_0
SPIA_TX64_EOP_0
SPIA_TX64_ERR_0
SPIA_TX64_WE_0 SPIA_TX64_PORT_0[7:0]
SPIA_TX64_WD_CNT_RST_ FPGA Core Line Write Termination indicator. This signal causes the FIFO write address 0 pointer within the embedded core to increment to the next address location for the addressed partition. This signal can be used for custom applications as well as for diagnostic test functions.
Note: For SPIB replace A with B
35
Lattice Semiconductor
Table 3. SPIA Core Transmit FPGA Interface in 64-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_TX64_LINK_DIS_0 Direction From/To
ORCA ORSPI4 Data Sheet
Description
FPGA Core Link disable control signal. When asserted to a logic '1', the AMA will cease polling from a DPRAM. All ports associated with a disabled DPRAM will remain unserviced until the control signal is deasserted. The AMA will send IDLE data across the SPI4 link. If the application continues to write data to that port FIFO, it will eventually fill and provide proper FIFO fill status to the application. FPGA Core Transmit write reference clock. The clocks across the different transmit interfaces are independent from each other, and are not required to be synchronous to each other. Core FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX64_ADDR_1[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the configured fill level within the partition. FPGA Core Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum of eight partitions. When operating in 64-bit mode, each partition will be 2x the depth of the corresponding partition in 32-bit mode. More than one port can be configured to share a virtual FIFO partition. FPGA Core User Write data. Two writes are required in order to complete an entire 128bit line. All writes must occur in two write bursts, unless an EOP occurs. FPGA Core Byte enables indicating which bytes within the 64-bit word are valid. Bit[7]-Byte enable for SPIA_TX64_DATA_0[63:56] Bit[6]-Byte enable for SPIA_TX64_DATA_0[55:48] Bit[5]-Byte enable for SPIA_TX64_DATA_0[47:40] Bit[4]-Byte enable for SPIA_TX64_DATA_0[39:32] Bit[3]-Byte enable for SPIA_TX64_DATA_0[31:24] Bit[2]-Byte enable for SPIA_TX64_DATA_0[23:16] Bit[1]-Byte enable for SPIA_TX64_DATA_0[15:8] Bit[0]-Byte enable for SPIA_TX64_DATA_0[7:0] If no BE bits are asserted for a particular location within the DPRAM, data will be dropped and no write to the DPRAM will occur. According to the SPI-4.2 specification, the BE bits must be asserted for all but the last transfer, where an End of Packet or Error may occur. The valid combinations of BE are as follows: BE[7:0] = 11111111--indicates all eight bytes contain valid user data. If an EOP is present, it resides within the eighth byte. BE[7:0] = 11111110--indicates seven bytes are valid. EOP occurs in seventh Byte. BE[7:0] = 11111100--indicates six bytes are valid. EOP occurs in sixth Byte. BE[7:0] = 11111000--indicates five byte is valid. EOP occurs in fifth Byte. BE[7:0] = 11110000--indicates four bytes are valid. EOP occurs in fourth Byte. BE[7:0] = 11100000--indicates three bytes are valid. EOP occurs in third Byte. BE[7:0] = 11000000--indicates two bytes are valid. EOP occurs in second Byte. BE[7:0] = 10000000--indicates one byte is valid. EOP occurs in first Byte. Start of Packet indicator. A '1' indicates the start of packet for a particular FPGA Core port. When operating in 64-bit mode, the SOP indicator must be asserted coincident with the first write per address line within the FIFO partition. End of Packet indicator. A '1' indicates the end of packet for a particular FPGA Core port. The EOP may be asserted on either write per address line within the FIFO partition.
0
SPIA_TX64_CLK_0
SPIA_TX64_FIFO_FULL_0
SPIA_TX64_ADDR_1[2:0]
SPIA_TX64_DATA_1[63:0] SPIA_TX64_BE_1[7:0]
1
SPIA_TX64_SOP_1
SPIA_TX64_EOP_1
Note: For SPIB replace A with B
36
Lattice Semiconductor
Table 3. SPIA Core Transmit FPGA Interface in 64-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_TX64_ERR_1 Direction From/To
ORCA ORSPI4 Data Sheet
Description
Packet error indication. A '1' indicates an error has occurred for the current packet being transmitted. The ERR signal must be asserted coincident with the EOP signal. FPGA Core When an EOP is detected by the DPRAM Write Pointer Logic, the address pointer will be automatically incremented to the next location within the FIFO partition range. FPGA Core FPGA Core FPGA Core Write Enable. A logic '1' causes data on the SPIA_TX64_DATA_1[63:0] bus to be captured for a write to the DPRAM. SPI4 port indicator, used to associate the current transmit data with a particular port number. Line Write Termination indicator. This signal causes the FIFO write address pointer within the embedded core to increment to the next address location for the addressed partition. This signal can be used for custom applications as well as for diagnostic test functions.
SPIA_TX64_WE_1 SPIA_TX64_PORT_1[7:0] SPIA_TX64_WD_CNT_RST_ 1 1 SPIA_TX64_LINK_DIS_1
Link disable control signal. When asserted to a logic '1', the AMA will cease polling from a DPRAM. All ports associated with a disabled DPRAM will remain unserviced until the control signal is deasserted. The AMA will send FPGA Core IDLE data across the SPI4 link. If the application continues to write data to that port FIFO, it will eventually fill and provide proper FIFO fill status to the application. Transmit write clock reference. The clocks across the different transmit FPGA Core interfaces are independent from each other, and are not required to be synchronous to each other. FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX64_ADDR_1[2:0] bus. This signal will be Core FPGA asserted to a logic '1' when the current FIFO partition has crossed the configured fill level within the partition. Port number of the currently serviced SPI4 data port. The value can either Core FPGA be the actual SPI4 value or a programmed user value. Further details are provided in the TX Calendar Control Logic description. Status of the SPI4 port currently being serviced. These signals can be Core FPGA used in conjunction with the FIFO partition FIFO to police transmit traffic congestion for a particular SPI4 port. Indicates the number of SPI4 cycles the currently active port will be serCore FPGA viced. Each cycle indicates an attempt to read 128 bits of data from the respective FIFO partition. FPGA Core Transmit reference clock. This clock signal is 1/4th the SPI4 clock. This signal can be used to synchronize FPGA application logic to the FPSC logic.
SPIA_TX64_CLK_1
SPIA_TX64_FIFO_FULL_1
SPIA_TX64_PORT_ID[7:0]
SPIA_TX64_STAT[1:0] Status /Os
SPIA_TX64_BURST_VAL[3:0]
SPIA_TREFCLK_X8 SPI_SATM_A Misc. I/Os
FPGA Core `0' - Incoming ATSCLK is assumed to be edge-aligned with the data and centered to the data eye within the chip. `1' - Incoming ATSCLK is assumed to be skewed with respect to the data off-chip.
Note: For SPIB replace A with B
Table 4. SPIA Core Transmit FPGA Interface in 128-Bit Mode
DPRAM FPGA Interface I/Os SPIA_TX128_ADDR[2:0] 0 SPIA_TX128_DATA[127:0] Direction From/To Description
Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum of eight partitions. When operating in 128-bit mode, each partition will be 4x FPGA Core the depth of the corresponding partition in 32-bit mode. More than one port can be configured to share a virtual FIFO partition. FPGA Core User Write data. A single write will complete an entire 128-bit line.
Note: For SPIB replace A with B
37
Lattice Semiconductor
Table 4. SPIA Core Transmit FPGA Interface in 128-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_TX128_BE[15:0] Direction From/To
ORCA ORSPI4 Data Sheet
Description
0
Byte enables indicating which bytes within the 128-bit word are valid. Bit[15]-Byte enable for SPIA_TX128_DATA[127:120] Bit[14]-Byte enable for SPIA_TX128_DATA[119:112] Bit[13]-Byte enable for SPIA_TX128_DATA[111:104] Bit[12]-Byte enable for SPIA_TX128_DATA[103:96] Bit[11]-Byte enable for SPIA_TX128_DATA[95:88] Bit[10]-Byte enable for SPIA_TX128_DATA[87:80] Bit[9]-Byte enable for SPIA_TX128_DATA[79:72] Bit[8]-Byte enable for SPIA_TX128_DATA[71:64] Bit[7]-Byte enable for SPIA_TX128_DATA[63:56] Bit[6]-Byte enable for SPIA_TX128_DATA[55:48] Bit[5]-Byte enable for SPIA_TX128_DATA[47:40] Bit[4]-Byte enable for SPIA_TX128_DATA[39:32] Bit[3]-Byte enable for SPIA_TX128_DATA[31:24] Bit[2]-Byte enable for SPIA_TX128_DATA[23:16] Bit[1]-Byte enable for SPIA_TX128_DATA[15:8] Bit[0]-Byte enable for SPIA_TX128_DATA[7:0] If no BE bits are asserted for a particular location within the DPRAM, data will be dropped and no write to the DPRAM will occur. According to the SPI-4.2 specification, the BE bits must be asserted for all but the last transfer, where an End of Packet or Error may occur. The valid combinations of BE are as follows: BE[15:0] = 1111111111111111--indicates all sixteen bytes contain valid user data. If an EOP is present, it resides within the sixteenth byte. BE[15:0] = 1111111111111110--indicates fifteen bytes are valid. EOP occurs in fifteenth Byte. BE[15:0] = 1111111111111100--indicates fourteen bytes are valid. EOP FPGA Core occurs in fourteenth Byte. BE[15:0] = 1111111111111000-indicates thirteen byte is valid. EOP occurs in thirteenth Byte. BE[15:0] = 1111111111110000--indicates twelve bytes are valid. EOP occurs in twelfth Byte. BE[15:0] = 1111111111100000-indicates eleven bytes are valid. EOP occurs in eleventh Byte. BE[15:0] = 1111111111000000--indicates ten bytes are valid. EOP occurs in tenth Byte. BE[15:0] = 1111111110000000--indicates nine bytes are valid. EOP occurs in ninth Byte. BE[15:0] = 1111111100000000--indicates eight bytes are valid. EOP occurs in eight Byte. BE[15:0] = 1111111000000000--indicates seven bytes are valid. EOP occurs in seventh Byte. BE[15:0] = 1111110000000000--indicates six bytes are valid. EOP occurs in sixth Byte. BE[15:0] = 1111100000000000-indicates five byte is valid. EOP occurs in fifth Byte. BE[15:0] = 1111000000000000--indicates four bytes are valid. EOP occurs in fourth Byte. BE[15:0] = 1110000000000000-indicates three bytes are valid. EOP occurs in third Byte. BE[15:0] = 1100000000000000--indicates two bytes are valid. EOP occurs in second Byte. BE[15:0] = 1000000000000000--indicates one byte is valid. EOP occurs in first Byte. Start of Packet indicator. A '1' indicates the start of packet for a particular port. When operating in 128-bit mode, the SOP indicator must be asserted FPGA Core coincident with the first line write to the FIFO partition in order to align the start of packet data with the SOP sideband signal.
SPIA_TX128_SOP
Note: For SPIB replace A with B
38
Lattice Semiconductor
Table 4. SPIA Core Transmit FPGA Interface in 128-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_TX128_EOP Direction From/To
ORCA ORSPI4 Data Sheet
Description
End of Packet indicator. A '1' indicates the end of packet for a particular port. FPGA Core When an EOP is detected by the DPRAM Write Pointer Logic, the address pointer will be automatically incremented to the next location within the FIFO partition range. FPGA Core Packet error indication. A '1' indicates an error has occurred for the current packet being transmitted. The ERR signal must be asserted coincident with the EOP signal. FPGA Core Write Enable. A logic '1' causes data on the SPIA_TX128_DATA_0[127:0] bus to be captured for a write to the DPRAM. FPGA Core SPI4 port indicator, used to associate the current transmit data with a particular port number.
SPIA_TX128_ERR
SPIA_TX128_WE SPIA_TX128_PORT[7:0]
0
SPIA_TX128_WD_CNT_RST FPGA Core Line Write Termination indicator. This signal causes the FIFO write address pointer within the embedded core to increment to the next address location for the addressed partition. This signal can be used for custom applications as well as for diagnostic test functions. SPIA_TX128_LINK_DIS_0 FPGA Core Link disable control signal. When asserted to a logic '1', the AMA will cease polling from a DPRAM. All ports associated with a disabled DPRAM will remain unserviced until the control signal is deasserted. The AMA will send IDLE data across the SPI4 link. If the application continues to write data to that port FIFO, it will eventually fill and provide proper FIFO fill status to the application. FPGA Core Transmit write reference clock. There is a single clock per SPI4 interface when operating in 128-bit mode. Core FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX128_ADDR[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the configured fill level within the partition. Core FPGA Port number of the currently serviced SPI4 data port. The value can either be the actual SPI4 value or a programmed user value. Further details are provided in the TX Calendar Control Logic description. Core FPGA Status of the SPI4 port currently being serviced. These signals can be used in conjunction with the SPIA_TX32_PORT_ID signal to police transmit traffic congestion for a particular SPI4 port.
SPIA_TX128_CLK SPIA_TX128_FIFO_FULL
SPIA_TX128_PORT_ID[7:0]
SPIA_TX128_STAT[1:0]
SPIA_TX128_BURST_VAL[3: Core FPGA Indicates the number of SPI4 cycles for which the currently active port will Status 0] be serviced. Each cycle indicates an attempt to read 128 bits of data from I/Os the respective FIFO partition. ATREFCLK_F SPIA_TREFCLK_X8 Core FPGA Transmit reference clock. This clock signal is 1/4th the SPI4 clock. This signal can be used to synchronize FPGA application logic to the FPSC logic. FPGA Core Quarter-rate Transmit reference clock. This FPGA-sourced clock reference must be 2x the desired Transmit SPI4 line clock rate. When not operating the Transmit SPI4 core in Quarter-rate mode, this signal should be tied off. Ex: For a 100 MHz Transmit SPI4 line clock, SPIA_TREFCLK_X8 from the FPGA must be 200 MHz. FPGA Core `0' - Incoming ATSCLK is assumed to be edge-aligned with the data and centered to the data eye within the chip. `1' - Incoming ATSCLK is assumed to be skewed with respect to the data off-chip.
SPI_SATM_A Misc. I/Os
Note: For SPIB replace A with B
39
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
I/O Modes - SPI4 FPGA/Embedded Core Data Protocol In order to successfully transmit data across the Transmit SPI4 link, there is a certain protocol that the data and control signals must obey. This section outlines the FPGA/embedded core interface protocol to follow for each of the operating modes of the Transmit SPI4 embedded core. As mentioned, there are three basic modes of operation when transmitting data into the embedded core from the FPGA. For all modes of operation, data is transferred synchronous to the rising edge of the respective SPI_TX_CLK signals. The following figures detail the write protocol defined for transmitting SPI4 transmit data. Figure 11 below shows basic interface signals for 32-bit mode of operation.
Figure 11. Basic 32-bit Data Write Protocol to DPRAM
1 SPIA_TX32_CLK SPIA_TX32_ADDR[2:0] SPIA_TX32_WE SPIA_TX32_DATA[31:0] SPIA_TX32_BE[3:0] SPIA_TX32_SOP SPIA_TX32_EOP SPIA_TX32_PORT[7:0] SPIA_TX32_WD_CNT_RST Note: SPIB is identical to SPIA Port 3 Port 3 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xC Partition Addr 'k' 2 3 4 5 6 7 8 9 10
During clock cycle 1, the FPGA asserts the partition Address, which indicates which partition within the DPRAM the data and control signals are to be written to. The Write Enable signal is also asserted, qualifying all data and control signals. In the figure, this is the start of a packet, so the SOP signal is also asserted. Data is presented to the interface, as well as the Byte Enable (BE) and Port ID signals. The Port ID is used to identify the PORT_ID field within the SPI4 control word. The BE vector is used to qualify which Bytes on the SPI4 transmit link are valid data. During clock cycle 4, the internal DPRAM write is automatically incremented, and the user is expected to continue write accesses to the FIFO partition. During clock cycle 8, the BE bits are set to 0xC, indicating only two of the four Bytes contain valid packet data. During clock cycle 8, the FPGA indicates an End of Packet condition for the current selected Port. Asserting the EOP signal causes the internal logic to terminate writes to the current Port, as well as automatically incrementing to the next address for the FIFO partition. The Port ID signal should be asserted during an entire write sequence. At a minimum, it must be asserted at least during the last write to the current DPRAM address line (i.e. for every 128 data bits that are in a DPRAM location). In the figure above, the Port ID must be asserted during clock cycles 4 and 8. Internal to the embedded core is logic that advances the write pointer for each DPRAM partition. Although not visible to the FPGA, the internal DPRAM pointer logic advances to the next valid address within partition range after every 4 writes when in 32-bit aggregation mode.
40
Lattice Semiconductor
Figure 12 shows 32-bit write timing using fast back-to-back transfers.
ORCA ORSPI4 Data Sheet
Figure 12. 32-Bit Write Protocol Using Fast Back-to-Back Transfers
1 SPI_TX32_CLK SPI_TX32_ADDR[2:0] SPI_TX32_WE SPI_TX32_DATA[31:0] SPI_TX32_BE[3:0] SPI_TX32_SOP SPI_TX32_EOP SPI_TX32_PORT[7:0] SPI_TX32_WD_CNT_RST Internal DPRAM Write Ptr. NOTE: SPIB is identical to SPIA Addr 'n' Addr 'm' 'm+1' Addr 'n+1' Port 3 Port 7 Port 3 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0x8 0xF 0xF Partition Addr 'k' Addr 'k+1' Addr 'k' 2 3 4 5 6 7 8 9 10 11
During clock cycle 1, the FPGA asserts the partition Address, which indicates which partition within the DPRAM the data and control signals are to be written to. The Write Enable signal is also asserted, qualifying all data and control signals. In the figure, this is the start of a packet, so the SOP signal is also asserted. Data is presented to the interface, as well as the Byte Enable (BE) and Port ID signals. The Port ID is used to identify the PORT_ID field within the SPI4 control word. The BE vector is used to qualify which Bytes on the SPI4 transmit link are valid data. During clock cycle 4, the FPGA has completed writing an entire 128-bit line to the addressed DPRAM partition and begins an access to another partition commencing with clock cycle 5. Since there was no EOP presented during clock cycle 4, Port 3 must be revisited later with the remaining packet data and required EOP. The internal DPRAM write is automatically incremented at the end of clock cycle 4 as well. During clock cycle 5, Port 7 is addressed as the destination partition for the next 128-bit line burst sequence. During clock cycle 8, the BE bits are set to 0x8, indicating only one of the four Bytes contain valid packet data. The EOP signal is also asserted during clock cycle 8 indicating the end of packet for the currently active Port 7. Asserting the EOP signal causes the internal logic to terminate writes to the current Port, as well as automatically incrementing to the next address for the FIFO partition. During clock cycle 10, the FPGA returns to Port 3, completing the packet with two 32-bit bursts, and asserting the EOP during the latter write cycle. All BE bits set to a logic `1' during the second write indicates all four bytes of the write are valid. As shown, data may be written to different Ports, in a fast back-to-back fashion, without any reduction in data throughput. Some points to note are: * According the SPI4 specification, the smallest packet that may be transmitted across the Transmit SPI4 link consists of a single 16-Byte transfer. This means a single occurrence of SOP and EOP may occur within any DPRAM location. * According to the SPI4 specification, only a single Port's data may occur within a 16-Byte cycle. As a consequence, data from a single Port is permitted to be written to any single 128-bit location within the DPRAM partitions. 41
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
* The SOP must always be written into the first byte location of the 16-byte DPRAM word. (Shown in Figure 7 for the 32-bit interface mode.) With the Lattice SPI4 interface, the EOP may occur during any of the four 4-byte mode writes to fill the 16-byte DPRAM, and will be associated with the correct 128-bit line within the partition memory. The next two figures show the 64-bit write protocol from the FPGA to the TX DPRAMs. It is functionally identical to the 32-bit mode, except two writes are required to fill an address line within a FIFO partition instead of four. Figure 13 shows the basic interface signals for 64-bit mode of operation.
Figure 13. Basic 64-Bit Data Write Protocol to DPRAM
1 SPIA_TX64_CLK SPIA_TX64_ADDR[2:0] SPIA_TX64_WE SPIA_TX64_DATA[63:0] SPIA_TX64_BE[7:0] SPIA_TX64_SOP SPIA_TX64_EOP SPIA_TX64_PORT[7:0] SPIA_TX64_WD_CNT_RST Note SPIB is identical to SPIA Port 3 Port 3 Port 3 0xFF 0xFF 0xFF 0xFF 0xFF 0xFE Partition Addr 'k' 2 3 4 5 6 7
During Clock cycle 1, the FPGA asserts the partition Address, which indicates which partition within the DPRAM the data and control signals are to be written to. The Write Enable signal is also asserted, qualifying all data and control signals. From the figure, this is the start of a packet, so the SOP signal is also asserted. Data is presented to the interface, as well as the Byte Enable (BE) and Port ID signals. The BE vector is used to qualify which Bytes on the SPI4 transmit link are valid data. When operating in 64-bit mode, there are 8 BE bits. During clock cycle 6 the BE bits are set to 0xFE, indicating 7 of the eight Bytes contain valid packet data. As with 32-bit mode, the Port ID signal should be asserted during an entire write sequence, although as a minimum it must be asserted at least during the second write to the current DPRAM address line. In the figure above, the Port ID must be asserted during clock cycles 2, 4, and 6. During clock cycle 6, the FPGA indicates an End of Packet condition for the current selected Port. Asserting the EOP signal causes the internal logic to terminate writes to the current Port. Also, the internal DPRAM pointer logic is advanced after every second write to the DPRAM when in 64-bit aggregation mode. As with the 32-bit aggregation mode, the "internal DPRAM Write Ptr" advances to the next valid address within partition range, but after every 2 writes when in 64-bit aggregation mode. This is because two 64-bit writes fill an entire 128-bit DPRAM line entry. The same interface logic in the FPGA can also be used as described in 32-bit mode, but the counter implemented in FPGA logic is simply a one-bit toggle FF.
42
Lattice Semiconductor
Figure 14. 64-Bit Write Protocol Using Fast Back-to-Back Transfers
1 SPI_TX64_CLK SPI_TX64_ADDR[2:0] SPI_TX64_WE SPI_TX64_DATA[63:0] SPI_TX64_BE[7:0] 0xFF SPI_TX64_SOP SPI_TX64_EOP SPI_TX64_PORT[7:0] SPI_TX64_WD_CNT_RST Internal DPRAM Write Ptr. Note: SPIB is identical to SPIA Addr 'n' Addr 'm' Port 3 Port 7 0xFF 0xFF 0xFF 0xFF Part. Addr 'k' Partition Addr 'k+4' 2 3 4 5
ORCA ORSPI4 Data Sheet
6
7
8
Part. Addr 'k'
0xFC
0xFF
0xC0
Port 3
'm+1'
'n+1'
As with Figure 13, the FPGA initiates the start of a packet by asserting the FIFO partition address, WE, Data and other pertinent control signals in Figure 14. During clock cycle 2, an entire 128-bit line has been written and the internal logic increments it's write pointer to the next location within the FIFO partition. During clock cycle 3, the FPGA begins writing to a different DPRAM FIFO using a back-to-back transfer. A new Partition address and Port ID are presented to the DPRAM. Since this is the Start of the Packet, the SOP is asserted. During clock cycle 5, the internal write pointer is advanced to the next address within the FIFO partition range. On clock cycle 6, the FPGA terminates the packet by asserting the EOP signal. The internal DPRAM Write Pointer advances during clock cycle 6 to the next location and then waits for the FPGA to attempt another write access to a partition within the DPRAM. Beginning with clock cycle 7, the FPGA resumes writing to the original port. The FPGA presents the correct Partition address and asserts the required control signals. The internal write pointer decodes the Partition address and sets the internal write pointer to address 'n+1'. As with 32-bit mode, in 64-bit aggregation mode, data may be written to different Ports in a fast back-to-back fashion without any reduction in data throughput. During clock cycle 8, the FPGA terminates writing to the current packet by asserting the EOP input signals and the correct number of BE signals. Figure 15 below shows the protocol required when operating in 128-bit aggregation mode. A single write from the FPGA fills an entire line within a FIFO partition.
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Figure 15. 128-Bit Write Protocol
1 SPIA_TX128_CLK SPIA_TX128_ADDR[2:0] SPIA_TX128_WE SPIA_TX128_DATA[127:0] SPIA_TX128_BE[7:0] SPIA_TX128_SOP SPIA_TX128_EOP SPIA_TX128_PORT[15:0] SPIA_TX128_WD_CNT_RST NOTE: SPIB is identical to SPIA Port 3 Port 7 0xFFFF 0xFFF8 0xFFFF Part. Addr 'k' Addr 'j' 2 3 4
ORCA ORSPI4 Data Sheet
5
6
Partition Addr 'j+4'
0xFFFF
0xFFFF
Port 2
SPI4 Transmit Interface - Detailed Description
The FPGA transmit interface provides a simple FIFO-like interface, simplifying write accesses. Asserting the correct 3-bit address with the associated write enable signal causes transmit data and sideband control signals to be registered for writes to a FIFO partition within the DPRAMs. When addressing a particular FIFO partition within the DPRAM, the associated FIFO fill level of the addressed partition is immediately reflected back to the FPGA, enabling the user to monitor the current fill level of a particular partition. Based upon the configured fill level, a logic '1' on the FIFO_FULL signal will indicate either a 3/4-full condition or a completely full condition for the indexed partition. Transmit DPRAMs There are four DPRAMs referred to as banks 0, 1, 2 and 3. Each bank has a 32-bit data interface to the FPGA. Each DPRAM has its own individual write enable and write clock allowing it to be written by the FPGA application independently. Each DPRAM bank is configured by software to operate in either 32-bit, 64-bit or 128-bit aggregation mode. Every DPRAM bank is also configured to contain 1, 2, 4 or 8 virtual FIFOs. The user determines the number of FIFOs depending on the number of ports and buffer requirements for the ports as required by a given application. The programming of a DPRAM bank in 32-bit, 64-bit or 128-bit mode and programming of the number of virtual FIFOs within a DPRAM bank is done through software as shown in Table 8. Note that in 64-bit mode, DPRAMs 0 and 1 must be configured identically. The combined DPRAM pair is referred to as DPRAM "0". Similarly DPRAM pairs 2 and 3 must be configured identically. This combined DPRAM pair is referred to as DPRAM "2". In 128-bit mode, all DPRAMs must be configured identically. The combined DPRAM banks are collectively referred to as DPRAM "0". The aggregation modes can be used in five possible combinations as shown in Table 6. The size of the embedded data and control FIFOs for each mode is shown in Table 7. The user accesses a virtual FIFO using the 3-bit FIFO read address (refer to Table 2, Table 3, and Table 4) from the FPGA. Table 5 shows the indexed partition based upon the configured DPRAM partitioning and aggregation mode.
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Table 5. FIFO Address Based on Programmed Virtual FIFOs
SPI[A,B]_TX_ADDR[2:0] XXX 000 001 010 011 100 101 110 111 Description
ORCA ORSPI4 Data Sheet
Bits are ignored when the DPRAM is configured to support a single partition. (Device Select bits can be set to any value in single partition mode). Selects Partition 0 when the DPRAM is configured to support 2, 4 or 8 partitions. Selects Partition 1 when the DPRAM is configured to support 2, 4 or 8 partitions. Selects Partition 2 when the DPRAM is configured to support 4 or 8 partitions. Selects Partition 3 when the DPRAM is configured to support 4 or 8 partitions. Selects Partition 4 when the DPRAM is configured to support 8 partitions. Selects Partition 5 when the DPRAM is configured to support 8 partitions. Selects Partition 6 when the DPRAM is configured to support 8 partitions. Selects Partition 7 when the DPRAM is configured to support 8 partitions.
Table 6. Possible Combinations of Aggregation Modes
Mode Banks 0 to 3 in 32-bit aggregation mode Banks 0, 1 in 64-bit aggregation mode, Banks 2,3 in 64-bit mode Banks 0,1 in 64-bit mode, Banks 2 & 3 in 32-bit mode Banks 0,1 in 32-bit mode, Banks 2 & 3 in 64-bit mode All banks in 128-bit Bank 0 in 32-bit mode, Bank 1 in 64-bit mode or vice-versa Bank 2 in 32-bit mode, Bank 3 in 64-bit mode or vice-versa Valid Yes Yes Yes Yes Yes No No
Within the embedded core, data is quad-word aligned, and written to the DPRAMs only on 128-bit boundaries. When operating in 32-bit or 64-bit mode, with the exception of EOP terminated write accesses, either 4 or 2 write accesses, respectively, must be performed before the internal FIFO address pointer can be incremented to the next location. It is required for the FPGA to perform all data writes on 128-bit boundaries. Thus, the application will write entire "lines" to the DPRAM causing the internal address pointer to increment to the next location in memory. If the FPGA attempts to write to a FIFO partition within the DPRAM and none of the 16 BE bits are set, the data will not be written into the FIFO and the internal write pointers will not be advanced. This is done to prevent erroneous data from being sent across the SPI4 link, as well as optimize FIFO memory usage. Link Disable Under certain circumstances, the application may require the SPI4 interface to disable a particular DPRAM from being serviced. To accommodate this, the user can assert the proper 'Link Disable" (LINK_DIS) signal indicating to the DPRAM logic to stop service to a particular DPRAM. As long as the assertion of the LINK_DIS for a particular partition is asserted, all partitions within the associated DPRAM will not be serviced. If the application attempts to perform further writes to any of the disabled FIFO partitions, data will be accepted up to the point the FIFO becomes full. After the FIFO fills, data will no longer be accepted. Data written to the disabled DPRAM will remain latent within the memory. Upon removal of the Link Disable signal, ports from the enabled DPRAM will be serviced according to the configured Calendar sequence. The following is an example of the effect of asserting a Link Disable. For this example, assume the ORSPI4 is configured as follows:
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- Both SPI-4 A and B are enabled - 32-bit aggregation for all banks Furthermore, assume the configuration of the SPI-4 is as follows: - - - -
ORCA ORSPI4 Data Sheet
Transmit calendar has 4 ports: 0,1, 2, and 3 Transmit DPRAMs configured to 1 partition each Transmit PDM assigns burst value of 4 to each port Transmit PDM maps port 0 to bank 0, port 1 to bank 1, port 2 to bank 2, and port3 to bank 3
Figure 16 shows how the port polling changes when the link disable for bank 1 is asserted (input signal SPIB_TX32_LINK_DIS_1 in this configuration). Before SPIB_TX32_LINK_DIS_1 is asserted, the normal port polling sequence - 0, 1, 2, 3, 0, 1, 2, 3, 0, .... - is seen on the SPIB_TX32_PORT_ID outputs. Each port poll lasts for the programmed burst value (4 in this example) number of cycles. After the SPIB_TX32_LINK_DIS_1 high transition, the sequence of port IDs changes to 0, 2, 3, 0, 2, 3, 0, ..... Note that the duration of port 0 is now 6 cycles with port 1 disabled. The 2 extra cycles are needed by the port poll sequencer to skip over port 1 and continue to port 2. The port poll sequencer does not read data from bank 0 during these 2 extra cycles, so they may be considered idle cycles. Before SPIB_TX32_LINK_DIS_1 was asserted, the port polling period was 4 ports X 4 cycles/port = 16 cycles. After SPIB_TX32_LINK_DIS_1 is asserted, the port polling period becomes 3 ports X 4 cycles/port + 2 extra cycles = 14 cycles.
Figure 16. Port 1 Disable
SPIB_TX32_CLK_0
SPIB_TX32_LINK_DIS_0
SPIB_TX32_LINK_DIS_1
SPIB_TX32_LINK_DIS_2
SPIB_TX32_LINK_DIS_3
SPIB_TX32_PORT_ID[7:0]
0
1
2
3
0
1
2
3
0
2
3
0
2
Figure 17 shows how the port polling changes when a second bank is disabled. Here the signal SPIB_TX32_LINK_DIS_2 is asserted to disable port 2. The port polling period with two ports disabled becomes 2 ports X 4 cycles/port + 4 extra cycles = 12 cycles.
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Figure 17. Port 1 and 2 Disable
SPIB_TX32_CLK_0
ORCA ORSPI4 Data Sheet
SPIB_TX32_LINK_DIS_0
SPIB_TX32_LINK_DIS_1
SPIB_TX32_LINK_DIS_2
SPIB_TX32_LINK_DIS_3
SPIB_TX32_PORT_ID[7:0]
0
2
3
0
2
3
0
3
0
3
0
TX DPRAM The TX DPRAMs consist of four 256 x 160 memories, that can each be partitioned into a maximum of 8 equally sized virtual partitions, providing a maximum of 32 virtual FIFO partitions. By providing a simple FIFO-like interface to the FPGA, the FPGA can access FIFO partitions by asserting a 3-bit address field. Internal logic maintains both write and read pointers and provides a programmable FIFO_FULL flag to the FPGA logic in order to prevent overflow conditions. Data may be written into the DPRAMs using either multiple 32-, or 64-bit interfaces, or alternatively using a single 128-bit interface. The sideband control bus is present for each individual interface. The DPRAM partition depths are a function of the interface width used, as well as the number of configured partitions. Table 7 shows the depth of virtual partitions for data and sideband control information based upon the write interface width and the number of partitions.
Table 7. Memory Size for Each Aggregation Mode and Partitioning
# of Configured Virtual FIFO Partitions 1 32-bit 2 4 8 1 64-bit 2 4 8 1 128-bit 2 4 8 DATA FIFO Depth (in Bytes) 2K 1K 512 256 4K 2K 1K 512 8K 4K 2K 1K Control FIFO Depth (in Bytes) 512 256 128 64 1K 512 256 128 2K 1K 512 256
Write Interface Mode
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ORCA ORSPI4 Data Sheet
Partitioning of the Dual Port RAMs is done through customer programmable registers. Table 8 below shows Register Settings for Aggregation Mode and Partition Size.
Table 8. Register Settings for Aggregation Mode and Partition Size.
DPRAM Aggregation Mode Address 30903 (SPIA), 30A30 (SPIB) DPRAM 0 (register Bits 0:1) = 00 Virtual FIFO Partition Size Address 30927 (SPIA), 30A27 (SPIB) Register Bits 0:1 = 00 01 10 11 00 01 01 10 11 00 10 01 10 11 Register Bits 2:3 = 00 DPRAM 1 (Register Bits 2:3) = 00 01 10 11 00 01 01 10 11 00 10 01 10 11 Register Bits 4:5 = 00 DPRAM 2 (Register Bits 4:5) = 00 01 10 11 00 01 01 10 11 00 10 01 10 11
Configuration 32-bit data width, partition size 1 32-bit data width, partition size 2 32-bit data width, partition size 4 32-bit data width, partition size 8 64-bit data width, partition size 1 64-bit data width, partition size 2 64-bit data width, partition size 4 64-bit data width, partition size 8 128-bit data width, partition size 1 128-bit data width, partition size 2 128-bit data width, partition size 4 128-bit data width, partition size 8 32-bit data width, partition size 1 32-bit data width, partition size 2 32-bit data width, partition size 4 32-bit data width, partition size 8 64-bit data width, partition size 1 64-bit data width, partition size 2 64-bit data width, partition size 4 64-bit data width, partition size 8 128-bit data width, partition size 1 128-bit data width, partition size 2 128-bit data width, partition size 4 128-bit data width, partition size 8 32-bit data width, partition size 1 32-bit data width, partition size 2 32-bit data width, partition size 4 32-bit data width, partition size 8 64-bit data width, partition size 1 64-bit data width, partition size 2 64-bit data width, partition size 4 64-bit data width, partition size 8 128-bit data width, partition size 1 128-bit data width, partition size 2 128-bit data width, partition size 4 128-bit data width, partition size 8
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DPRAM Aggregation Mode Address 30903 (SPIA), 30A30 (SPIB) DPRAM 3 (Register Bits 6:7) = 00
ORCA ORSPI4 Data Sheet
Virtual FIFO Partition Size Address 30927 (SPIA), 30A27 (SPIB) Register Bits 6:7 = 00 01 10 11 00 01 10 11 00 01 10 11
Configuration 32-bit data width, partition size 1 32-bit data width, partition size 2 32-bit data width, partition size 4 32-bit data width, partition size 8 64-bit data width, partition size 1 64-bit data width, partition size 2 64-bit data width, partition size 4 64-bit data width, partition size 8 128-bit data width, partition size 1 128-bit data width, partition size 2 128-bit data width, partition size 4 128-bit data width, partition size 8
01
10
Based upon the traffic characteristics of individual ports and number of ports supported, the user can tailor the FIFO depth to optimize performance at the FPGA/embedded core interface. When operating in 32-bit mode, four write cycles are necessary to complete an entire 128-bit line. 64-bit mode requires 2 write accesses, with 128-bit mode using a single clock per line fill. When data is read out of the DPRAMs, via the AMA logic, it is read using a 128-bit data bus. Therefore, for each port serviced, one clock cycle is consumed to read 16 data Bytes and 4 control Bytes from each addressable location within a FIFO partition. This corresponds to the SPI4 requirement that only a single SPI4 port's data may exist on the transmit data bus within any Burst Cycle. A Burst Cycle is made up of 16 Bytes. Note, for all modes of aggregation, if an entire 128 bits is written to any FIFO partition, with all 16 BE bits deasserted, the Quad-word will not be written to the DPRAM, nor will the internal write pointer be incremented for the selected FIFO partition. Within the Transmit DPRAM, there are user-programmable fill level thresholds for each enabled partition. The programmable levels are either 3/4-full or absolutely full. When the fill level of an addressed partition exceeds the programmed fill level, a FIFO full condition is reported back to the FPGA. Because the fill level operates only on 128 bits, the full flag is only updated after an entire line has been written. The full condition will persist until the FIFO has been serviced and the fill level drops below the programmed fill threshold. In order to take a DPRAM temporarily out of service without updating the Calendar, the FPGA can assert the Link Disable (SPI_TX_LINK_DIS[3:0]) input signal associated with the DPRAM to be disabled. The FPGA is permitted to continue to write data to the disabled port FIFO, as it will obey all the functionality described above regarding FIFO fill level and status. When the DPRAM is to be put back into service, the user simply deasserts the LINK_DIS signal. The associated ports will then be serviced according to the configured Calendar sequence. Address Map Arbiter (AMA) Logic Block The Address Map Arbiter (AMA) logic block is a slave device to the TX Calendar Control logic. Upon receiving a valid AMA_ID and BURST_VAL vectors, the AMA will attempt to read out data from the indexed DPRAM FIFO partition along with the associated sideband control signals. In order to take a DPRAM temporarily out of service without updating the Calendar, the FPGA can assert the Link Disable (SPI_TX_LINK_DIS[3:0]) input signal associated with the DPRAM to be disabled. The FPGA is permitted to continue to write data to the disabled port FIFO, as it will obey all the functionality described above regarding
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ORCA ORSPI4 Data Sheet
FIFO fill level and status. When the DPRAM is to be put back into service, the user simply deasserts the LINK_DIS signal. The associated ports will then be serviced according to the configured Calendar sequence. Upon receiving a valid AMA_ID, the AMA logic will service a port by reading data from the FIFO partitions for BURST_VAL clock cycles. Both data and sideband control signals are read and sent directly to the TDP logic block. In the event a FIFO partition becomes depleted before BURST_VAL number of reads is performed, the AMA will send Idle data to the TDP and will override the associated Byte Enable (BE) control signals, indicating the current data is not user data. This will temporarily reduce the SPI4 transmit link data throughput, but will not affect the operation of the Transmit link itself. When reading data from FIFO partitions, and the FIFOs are empty, it is possible to gain back some lost data throughput on the SPI4 Transmit link. Enabling the TX_BURST_TERMINATION control register within the embedded core causes the AMA to advance to the next port for service within four clock cycles after detecting the FIFO is empty. This feature works in conjunction with the TX Calendar Control logic. Upon detecting the currently serviced FIFO has run empty, the AMA block sends a control signal to the Calendar Control logic, which then immediately advances to the next location within the Calendar and presents a new set of AMA_ID and BURST_VAL fields to the AMA block. Because there is a four-clock latency between detection of an empty FIFO and the assertion of the next port to service, data bandwidth gains can be achieved on ports with larger BURST_VAL values. Transmit Data Protocol (TDP) Logic Block The Transmit Data Protocol (TDP) block is responsible for receiving and formatting SPI4 packet data and all associated sideband control signals, and formatting the data into the correct SPI4 protocol. This block also performs DIP-4 calculation, SPI4 data word, control word and Training control word generation. Additionally, this block attempts to perform bandwidth optimization by combining ordered Bytes from 2 consecutive 128-bit words from the AMA whenever possible. This is done to maximize data throughput on the Transmit SPI4 link. The TDP provides a small FIFO to allow for data buffering in order to concatenate valid Bytes with idles. In the event the FIFO becomes full, it sends a FIFO_FULL flag to the Transmit Calendar Control Word logic to throttle data transmission. Flow control is necessary for small periods of time while Training patterns are being sent across the Transmit SPI4 link. Data formatting performed in this block consists of alignment, DIP-4 calculation and training pattern generation. Aligner: Using the SOP, EOP and Port control signals the TDP determines what type of control word is necessary to be transmitted with the corresponding data. Using the BE bits, the TDP can determine how to concatenate data into sequences of continuous 16 Byte bursts whenever possible. DIP-4 Calculation: After aligning the data and control words, the TDP calculates the odd parity codeword according to the OIF SPI4 specification. Training Pattern Generation: There are two causes of generating a Training sequence for the Transmit SPI4 link: * Using the user-programmable TX_DATA_MAX_T register, or * The TDP receives four or more consecutive '11' patterns from the status block, indicating excess DIP-2 errors. Using the programmed TX_DATA_MAX_T register along with the user-programmable TX_ALPHA register, the TDP internally counts down the correct number of clock cycles before transmitting training sequences across the Transmit link. The TX_ALPHA register is used to indicate the number of Training sequences to be sent. When the Transmit status receives excessive errors, the status block sends consecutive '11' patterns to the TDP. According to the SPI4 specification, the TDP will begin sending training patterns across the SPI4 link until the status error is remedied.
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ORCA ORSPI4 Data Sheet
Transmit Data Output (TDO) Logic Block The Transmit Data Output (TDO) block contains the high-speed serializer, which uses an x8 clock, synthesized by an internal PLL, to generate the high-speed data from the low-speed 128-bit data. Data is transmitted off-chip using a 16-bit LVDS data bus TDAT[15:0], a LVDS control bit TCTL and a source synchronous clock TDCLK. The 16-bit data bus and control are DDR signals relative to the TDCLK. The LVDS buffers contained within the TDO are fully compliant with SPI4 electrical specifications. The TDO uses the internal embedded core transmit reference clock (TREFCLK) to generate an x4 TDCLK. The TDCLK and TREFCLK are both derived from the user-provided reference clock. The TREFCLK is used as the system clock for the entire Transmit SPI4 interface logic. The TREFCLK is also sent to the FPGA for the customer to use as a synchronizing signal source if desired. In order to support 10 Gbits/s throughput, the minimum frequency of TDCLK needs to be 622 Mbits/s (311 MHz DDR). For applications that require less than 100 - 200 Mbits/s on TDCLK, the PLL in the TDO block can be bypassed. This allows for operation as low as 100 MHz on the Transmit SPI4 link.
Figure 18. Transmit Calendar and Status Block
k = 32, 64, or 128 AMA_ID SPI[A,B]_TX_k_PORT_ID
8 2
To AMA
BURST_VAL TLSTAT TLSCLK
From External I/O TSI
ATSTAT ATSCLK
To FPGA I/F
SPI[A,B]_TX_k_STAT
SPI[A,B]_TX_k_BURST_VAL 4
TX CALENDAR PORT_ID TSP Control PORT_STAT Logic
Note: SPIA is identical to SPIB
Transmit Calendar (TCC) Logic Block The Transmit Calendar Block (TCC) is responsible for maintaining the transmit main and shadow calendars, providing port service information to the AMA, integrating transmit status update information into the servicing of ports according to the SPI4 specification, and providing port service information to the FPGA for traffic monitoring.
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Figure 19. Transmit Calendar Control Logic Functional Diagram
SPI[A,B]_TX_PORT_ID SPI[A,B]_TX_STAT Transmit Port Seq Addr SPI[A,B]_TX_BURST_VAL Calendar Main/ Port Desc Data TO FPGA
ORCA ORSPI4 Data Sheet
0
Shadow
TO AMA BURST_VAL AMA_ID
Port Descriptor Memory
STATUS UPDATE LOGIC
PORT_ID PORT_STAT
255
CREDIT MB_EN M BURST_VAL PORT_ID AMA STATUS
BANK_ID
PARTITION_ID
The Transmit SPI4 interface contains both main and shadow Calendars enabling a hitless switch over between an old and new Calendar schedule. Each Calendar is 1023 locations deep, providing a high degree of flexibility and customizable port service algorithms. The user can configure the Calendar(s) through software configuration registers. (See the transmit memory map register set for identification of individual configuration register addresses). NOTE, in order to effect a hitless switch at the logical port level, the user must ensure that port data associated with any Calendar modifications have been terminated correctly before the Calendar switches. For example, if the Shadow Calendar eliminates Port 3 from the Calendar sequence, the user must ensure there is no data associated for Port 3 in the FIFO partitions when the Calendar switches. Otherwise, service will be granted for an out-of-service port, causing higher layer protocol exceptions. The Calendar length is also configurable to indicate the number of valid port entries. Programming the CALENDAR_LEN register indicates how many entries within the Transmit Calendar are enabled for sequencing. Since the Calendar is 1023 locations deep, a single port may be serviced more than once per Calendar sequence. Port Service Information The TCC sequentially runs through the Calendar sequence retrieving the port number that is to be serviced next. The field is an 8-bit vector, supporting the entire 256 possible entries of the SPI4 Calendar. The retrieved port number is used to index a Port Descriptor Memory (PDM) to retrieve all pertinent information required for maintaining proper port servicing. There are several fields within the PDM that are required to be configured by the user before the Transmit interface can be enabled. A description of the fields within the descriptor is given below: * PORT_ID - Port information sent to the FPGA when a port is being serviced. This value is configurable by the user and can contain either the SPI4 number of the port, or can contain an alias the FPGA uses to map proprietary interface channels to the corresponding SPI4 port (See the 'M'-bit description below). The FPGA logic can also use the Port_ID for status acquisition, or other link layer flow control functions. After reset this field defaults to a value of 8'h00. * BURST_VAL - Port information sent to the FPGA (when a port is being serviced) and AMA. This user-configurable field indicates the maximum number of 16-Byte burst accesses the port is permitted to consecutively transmit across the SPI4 link, before segmentation must be performed. The FPGA can use this field to indicate how much data to source for the port being polled to maintain buffering within the DPRAM FIFO partition. After reset this field defaults to a value of 4'h0.
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ORCA ORSPI4 Data Sheet
* AMA - This user configurable field consisting of a DPRAM BANK_ID (left-most two bits) and a DPRAM PARTITION_ID, indicates to the AMA (AMA_ID) which physical DPRAM partition address to poll for port servicing. After reset, this field defaults to a value of 5'h00. * M - Indicates whether the programmed Port_ID or the SEQ_PORT_NUM contained within the Calendar Sequence Table should be broadcast to the FPGA. This is performed on a per port basis, providing a mapping function between proprietary FPGA port mapping and the SPI4 Transmit Calendar port number. EX: SPI4 Port Number 138 maps to FPGA interface Device #7, Port #17. When the 'M'- bit is set to a logic one, the programmed Port_ID (i.e. 138) is broadcast to the FPGA for the port being serviced; when set to a logic zero, the Port number from the Transmit Calendar is sent to the FPGA for that particular port. After reset, this field should default to a value of 1'b0. * Credits - Indicates the number of bursts the port is permitted to transmit across the SPI4 link between status updates, for that particular port. This field is updated with calculated credit values after the port is serviced. Whenever the receive status from the TSP block presents a port status value of 2'b11, the Credit field for the indexed port is to be cleared to a value of 10'h000. This disables the port. The user may configure an initial value for each enable port. After reset, this field is to default to a value of 10'h000. This field should not be altered after the Transmit Calendar is placed in operation. * MB_EN - This user-configurable register indicates whether the associated port supports MAX_BURST parameters as defined within the SPI4 specification. The Transmit Calendar supports a single TX_MAX_BURST1 and a single TX_MAX_BURST2 value. Logic one indicates that the configured port supports MAX_BURST. After reset, this field is to default to a value of 1'b0. This is configurable on a per-port basis. * STAT - Contains Transmit FIFO status from the TSP block. Used in conjunction with the MB_EN field to update the Credit field for the indexed port. Also sent to the FPGA for status monitoring. After reset this field is set to a value of 2'h3, indicating the port is disabled. Status Update Logic Transmit status is received from the TSP block (described later). Both the port number and associated status of the port is sent to the Status Update Logic. This block ensures that the status for each port, as it is received, is updated correctly. The status is received according to the programmed far-end Calendar, and will generally be received asynchronously (relative to port servicing) to the local Transmit Calendar polling. By providing the BURST_VAL, Stat, and Port_ID value to the FPGA, application logic can maintain the required data bandwidth it needs to source, in order to keep the respective FIFO partition from over/under-flowing. These signals can also be used in conjunction with FPGA control logic to oversee the operation of the Memory Controller for accessing the Transmit SPI4 port data. Transmit Status Input (TSI) Block The Transmit Status Input (TSI) block provides the interface to the SPI4 Transmit Status Signals. These signals can be either LVDS or LVCMOS input buffers. This is selected using the SPI4_STATUS_IO_SEL register setting. The Status interface supports quarter-rate mode only, as defined within the SPI4 specification. The user has the option to use the status input signals either in phase with status input clock, or out of phase with the status input clock, by optionally inverting the input clock signal on-chip. Setting SPI_SATM_A and SPI_SATM_B registers to a "1" will cause them to be in phase, setting to a "0" will cause them to be out of phase. The TSI block receives transmit status and provides both the status information and a derived clock to the TSP block. Transmit Status Protocol (TSP) Block The Transmit Status Protocol (TSP) block receives status from the TSI block and uses the user-configured transmit calendar to associate the current received status with a port. This block performs FIFO status decoding, buffering and DIP-2 calculations. As defined within the SPI4 specification, if DIP-2 errors occur, it sends an error flag to the TDP block for processing. The TSP provides port status information to the Transmit Calendar logic along with the associated port number. The Calendar logic then updates the appropriate Port STAT field. The TSP block also supports Hitless Bandwidth Provisioning as defined within Appendix G of the SPI4 specification.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Transmit Calendar Operation This section gives a description of how the Transmit Calendar operates, in order to assist users in understanding how to configure the TX SPI4 programmable Calendar and configuration registers to fit their application. Figure 18 and Figure 19 will be used as reference. The Transmit Calendar logic is synchronous to TREFCLK for it's internal operations. The Transmit Calendar logic uses an indirect addressing scheme to acquire port sequence information. This enables the user to configure the Calendar easily, while minimizing the amount of information that needs to be programmed within the Calendar table. Indirect addressing also enables users to configure the entire Port Descriptor Memory at initialization time, without having to actually enable all the entries. The user has access to modify port information within the PDM at any time, whereas the Calendar(s) can only be updated while it is not in service. The Transmit Calendar sequentially runs through all the user-enabled port entries within the 1K memory. The Calendar rolls over to the first entry whenever the user-configured maximum Calendar length is reached. The time between polling the same port is a function of the several factors, including user-configured BURST_VAL per port, and whether the TX_BURST_TERMINATION is enabled (set to LOGIC "1"). * The user must configure the TX_CAL_LEN_MAIN to indicate the number of valid entries to sequence through in the Main Calendar. Not all applications require 1023 locations to be polled. * If the Shadow Calendar is to be used, the user must configure the TX_CAL_LEN_SHD to indicate the number of valid entries to sequence in the Shadow Calendar. The Shadow Calendar is independent of the Main Calendar, and may have a different number of entries. * The user must either enable TX_BURST_TERMINATION or leave it disabled. By default it is disabled. When a port is indexed within the Calendar, the indexed vector serves as the address to the Port Descriptor Memory, to fetch all the necessary information to service the selected port. The Port Descriptor Memory (PDM) provides 256 entries; one for each possible SPI4 port. The PDM contains all the port servicing control information. When a port is indexed via the Calendar, the Calendar pointer is incremented to the next location, serving as a pseudo prefetch in case TX_BURST_TERMINATION is enabled. Every time a Port is indexed in the PDM, an internal counter loads BURST_VAL and begins decrementing. Upon nulling out, the next Calendar entry is used to index the PDM to fetch the next port to be serviced. Again, the Calendar advances to the next enabled location. As defined within the SPI4 specification, BURST_VAL indicates the number of 16-Byte cycles a port may be serviced before segmentation must occur. Using BURST_VAL, the Transmit Calendar can maintain constant Port servicing from the Dual Port memories. * The user must configure a BURST_VAL value for each enabled SPI4 port. The PDM contains 256 locations, i.e. one for each possible SPI4 port. The Transmit Calendar broadcasts the AMA_ID and BURST_VAL vectors, fetched from the PDM, to the AMA block. The AMA will use the ID value to address the physical entry of the port that is to be serviced. Note the AMA_ID value is the physical address of the DPRAM and is made up of two user-configurable fields, the PARTITION_ID and BANK_ID. * The DPRAMs consist of 4 banks, and each may be partitioned into a maximum of 8 virtual FIFOs each. The user must configure both the PARTITION_ID[2:0] and BANK_ID[1:0] fields for each enabled port within the PDM. The PARTITION_ID vector is identical to the SPIA_TX32_ADDR_0[2:0]. The user configures the same partition address for a particular port that is used as the address on transmit DPRAM write interface. The BANK_ID vector is simply derived from the physical interface used at the FPGA/embedded core interface, as shown below. - 32-bit mode [00,01,10,11], providing up to 4 interfaces - 64-bit mode [00, 01], providing up to 2 interfaces - 128-bit mode [00], providing a single interface For all combinations of aggregation, the values given above apply. * More than one port can be mapped to the same partition. Simply program the same PARTITION_ID and BANK_ID values in all the PDM port entries that share the same partition. 54
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
The Transmit Calendar also broadcasts the BURST_VAL, current status and either the transmit Calendar entry vector or a user-configurable port value to the FPGA. Selection between the Calendar vector and the configured value is decided with the 'M'-bit. When logic '0', the Calendar Port vector is broadcast to the FPGA. Otherwise, the user-configurable PORT_ID field is sent. The optional PORT_ID is provided in order to assist the FPGA in mapping it's proprietary channel/port numbers to the SPI4 Calendar port value. By configuring the PORT_ID value and setting the 'M'-bit for particular ports, the FPGA will receive the programmed value instead of the SPI4 port number. This feature is very useful when the user is sharing a particular FIFO partition within the DPRAM between multiple ports. Providing these fields to the FPGA enables users to updated statistics of port servicing for external data schedulers and the external Memory Controller. * If the user desires to have proprietary channel/port values broadcast to the FPGA, the 'M'-bit must be set to a logical "1", and the associated PORT_ID field must be configured to the desired value. * This is done on a per port basis, so some ports may be mapped, while others use the Transmit Calendar index vector. * If the user maps more than one port to the same FIFO partition, the user is free to choose which Port ID field is sent to the FPGA. As ports are serviced, their Credit fields are updated according to the requirements as defined within the SPI4 specification. Although not commonly used, the Transmit SPI4 Calendar logic allows the user to configure the Credit field with an initial value at configuration time. This is useful for some applications as well as providing diagnostic and test capabilities of the Calendar update logic. The Transmit Calendar also supports single Maxburst1 & Maxburst2 values, as defined within SPI4. The MB_EN field is enabled on a per-port basis and indicates whether the associated port differentiates between the defined Hungry and Starving states. When the MB_EN bit is set to a logical "1", that particular port uses both the Maxburst1 and Maxburst2 fields: otherwise only the Maxburst1 field is associated with the Port's Credit field update algorithm. * In order to use the Maxburst1 and Maxburst2 fields, the user must program both fields to the required values. By default the value for these registers is "0". * The user must either configure the MB_EN field for each port to a logical "1" if the port have it's Credit field updated using the Maxburst2 field. By default the Maxburst2 values are not used in the Credit update calculation. * The user can optionally configure the Credit field to a particular value if desired, although it is not necessary for most applications. During normal operation, Transmit status is received on a per port basis. The status field for each port is updated independent of where the Transmit Calendar polling exists. Internal logic prevents updates to be performed on a port while it is in use. Although uncommon, the SPI4 Transmit Calendar allows the user to configure the STAT field to some value, but only during initialization. This is intended to be used for diagnostics or for some other proprietary applications. Under normal operation, the user can ignore this function. * The user can program the STAT[1:0] field for as many ports as desired within the PDM. When a HUNGRY status indication is received, transfers up to Maxburst2 16-byte blocks or the remainder of what was previously granted (whichever is greater) may be sent to the corresponding port prior to the next status update. A STARVING status indication indicates that buffer underflow is imminent in the corresponding PHY port. When STARVING is received, transfers for up to Maxburst1 16-byte blocks may be sent to the corresponding port prior to the next status update. Internal to ORSPI4, the "16-byte blocks" term is also called BURST_VAL. Even though the Maxburst1 and Maxburst2 are global parameters for all the ports, each port has its own BURST_VAL parameter attached to it that the user must program in the Transmit Port Descriptor Memory (TXPDM). Every time the TX status is updated for a port, Maxburst1 or Maxburst2 values are loaded into the credits field for that particular port. From that point on until a new TX status update takes place, data is sent according to the following flow-chart.
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Lattice Semiconductor
Figure 20. Port Credit Field Update Flow Chart
START
ORCA ORSPI4 Data Sheet
NO
Tx STATUS UPDATE
YES
Data Sent = | (Credits - BURST_VAL) | * 128 Bits
HUNGRY STATUS
SATISFIED
MB_EN
NO
STARVING
Credits = | (Credits - BURST_VAL) |
YES
Credits = Maxburst1
Credits = Maxburst2
Data Sent = BURST_VAL * 128 Bits
Table 9 below shows the SPI4 Status update definitions.
Table 9. SPI4 Status Field Definition
MSB 1 1 LSB 1 0 Description: Reserved for framing or indicate a disabled status link. SATISFIED Indicates the corresponding port's FIFO is almost full. When SATISFIED is received, only transfers using the remaining previously granted 16-byte blocks (if any) may be sent to corresponding port until the next status update. No additional transfers to that port are permitted while SATISFIED is indicated. HUNGRY When HUNGRY is received, transfers for up to MAXBURST2 16-byte blocks or the remainder of what was previously granted (whichever is greater), may be sent to the corresponding port until the next status update. STARVING Indicates that buffer underflow is imminent in the corresponding PHY port. When STARVING is received, transfers for up to MAXBURST1 16-byte blocks may be sent to the corresponding port until the next status update.
0
1
0
0
When transmitting across the SPI4 link, typically for clock speeds in excess of 350 MHz, dynamic alignment is required to maintain a coherent data link. In conjunction with dynamic alignment, SPI4 outlines a Training protocol that is periodically used to maintain receive data integrity. The SPI4 Transmit core supports data training through the use of a 32-bit variable named TX_DATA_MAX_T. This 32-bit variable indicates the number of clock cycles that will occur between training sequences. SPI4 also defines an TX_ALPHA variable indicating the number of times the training pattern is to be repeated during a training session. The TDP supports both these variables allowing the user to tailor both of these parameters to fit their particular environment and dynamic traffic requirements. * The user must configure the 32-bit TX_DATA_MAX_T variable to indicate the number of clock cycles that should lapse between training sequence. A value of 0x00000000 disables training. By default training is disabled. 56
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
* If training is to be used, the user must also configure the 16-bit TX_ALPHA variable to indicate the number of times the training pattern is to be repeated. By default the value is 0x0000 which disables the training pattern. If the number of Bytes within the training sequences do not fill entire SPI4 Burst Cycle, the unused Byte fields will be padded with Idle data in order to keep the training sequences aligned on 16 Byte boundaries. Calendar Programming On a SPI4 link, FIFO status information is received periodically over the status link (TSTAT bus on the SPI4 interface) from the device that sources data. Calendar is a means by which the SPI4 link conveys information to the TX data source about the availability of buffer space in the RX FIFOs that receive data from that data source. A calendar is a sequence of status messages that: * Provides information on the buffer space for a port or traffic flow. * Allows user to allocate bandwidth for a port or flow depending on the overall traffic characteristics. The SPI4 status channel operates at 1/8th the SPI4 data rate, which is reasonable because data is always sent in 16-byte bursts. Thus, the fastest status update can be expected once in every 8 data clock cycles. For a given port, the frequency with which its status is reported to the far-end transmitter source depends on the allocated bandwidth for the port. It is imperative that the transmitter and receiver devices are programmed with identical calendar sequences. The following examples illustrate this: Suppose a channelized STS-48 has three STS-12 ports and four STS-3 ports (channels), each STS-12 port should have four times the bandwidth of an STS-3 port and 12 times the bandwidth of an STS-1 port within a single calendar cycle. The first step is to map each port to an 8-bit Port ID (address) as shown in Table 23
Table 10. Port ID Mapping
Port A1 A2 A3 B1 B2 B3 B4 Bandwidth STS-12 STS-12 STS-12 STS-3 STS-3 STS-3 STS-3 8-Bit Port ID (Port Address) 0x00 0x01 0x02 0x03 0x04 0x05 0x06
The calendar sequence is as follows: A1, A2, A3, B1, A1, A2, A3, B2, A1, A2, A3, B3, A1, A2, A3, B4 The number of calendar entries is thus 16. This calendar sequence is programmed in the transmit calendar memory as follows: * This example uses the main calendar. The calendar memory is selected by setting the TX_CAL_MEM_SEL bit (address 30917 in SPIA and address 30A17 in SPIB) to `1'. * Writes are done to addresses 0x31000 - 0x3100F. This will correspond to entries 0x00 - 0x0F in the calendar memory. This is shown in Table 11. Note that the main calendar memory has 1023 locations and can be programmed through addresses 0x31000 - 0x313FE. The shadow calendar memory also has 1023 locations and can be programmed through addresses 0x31400 - 0x317FE. * After programming the calendar memory, the TX_CAL_MEM_SEL bit is set to `0'. * The calendar length register TX_CAL_LEN_MAIN is set to 16 (address 30922 and 30923 in SPIA, 30A22 and 30A23 in SPIB).
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
* TX_CAL_M_MAIN (address 30921 in SPIA and 30A21 in SPIB) is set to the number of times the calendar sequence needs to be repeated between framing patterns. * The shadow calendar can be programmed in the same identical fashion as the main calendar using the steps described above. To enable hitless switching between main and shadow calendar memories, the TX_CAL_SW_EN bit (address 30916 in SPIA and 30A16 in SPIB) should be set to `1'. This will cause the transmit status logic to detect the calendar select word after the framing pattern. A "01" detected on the calendar select word selects the main calendar. A "10" on the calendar select word selects the shadow calendar. It is important to enable this feature in the receive device on the other end of the SPI4 link. If the receive device is a Lattice ORSPI4 device, this is done by setting RX_CAL_SW_EN bit (address 30916 in SPIA and 30A16 in SPIB) to `1'. This will cause the far-end receive status logic to insert the calendar select word after the framing pattern.
Table 11. Transmit Calendar Memory Contents
TX Calendar Memory Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f TX Calendar Memory Contents (Port ID) 0x00 0x01 0x02 0x03 0x00 0x01 0x02 0x04 0x00 0x01 0x02 0x05 0x00 0x01 0x02 0x06 Port Number A1 A2 A3 B1 A1 A2 A3 B2 A1 A2 A3 B3 A1 A2 A3 B4
MIN_BURST_MODE
The number of transmitted data bytes in a given port's SPI-4 data segment can be programmed by setting the BURST_VAL for a given port in the Port Descriptor Memory. In general, setting a port's BURST_VAL will result in transmitted data segments of length (16 * BURST_VAL) bytes. However, data segments shorter than (16 * BURST_VAL) bytes will occur about 15% of the time. There are three reasons for shorter data segments: 1. End-of-packet (EOP) causes segment to terminate 2. Insufficient data is written into a port's transmit FIFO to support a full data burst. 3. ORSPI4 core logic causes occasional short segments. Reason 1 will always naturally occur with any SPI4 link and so can never be completely eliminated. However, the following steps which take advantage of the MIN_BURST_MODE will eliminate short data segments caused by reasons 2 and 3: 1. Set MIN_BURST_MODE (address 30916, bit 3 for SPIA and 30A16, bit 3 for SPIB) to 1.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
2. It is recommended that BURST_VAL for all ports be set to the same value equal to (data_burst_value/16). For example, for a data burst requirement of 64 bytes, all port BURST_VAL should be set to 4. For a data burst requirement of 128 bytes, all port BURST_VAL should be set to 8. A maximum BURST_VAL of 15 will support a data burst of 240 bytes. Having a common BURST_VAL for all ports simplifies design of the sequencer needed to keep all transmit ports filled sufficiently at all times for data bursts. With all port BURST_VAL the same, relative port bandwidth can be set by loading the Transmit Calendar appropriately. 3. Set TX_FIFO_THRESHOLD_L (address 30945, bits [0:2] for SPIA, address 30A45, bits [0:2] for SPIB) to [integer(BURST_VAL/4) + 1]. For example, if BURST_VAL = 10, TX_FIFO_THRESHOLD_L should be set to 3. 4. Set MAXBURST1 and MAXBURST2 to integer multiples of BURST_VAL that are at least 2 times BURST_VAL. For example, if BURST_VAL = 4, then MAXBURST1 could be set to 12 and MAXBURST2 could be set to 8. To optimize a port for minimum bursts it is best to set MAXBURST1 and MAXBURST2 to as high a value as possible. The reason for this is as follows. Whenever the transmitter detects a SATIFIED status condition when polling a port, that port's credit field (stored in the Port Descriptor Memory) is automatically decremented by BURST_VAL. If the credit field ever drops below BURST_VAL, the port poll will terminate, reducing the available time to fill the transmit FIFOs for data bursts. Therefore, it is recommended that the SPI[A,B]_k_STAT signal from the core be monitored and writing be suspended to any port whose receive FIFO is SATISFIED. Writing to that port can commence once HUNGRY or STARVING appears at the SPI[A,B]_k_STAT because this will guarantee that the credit field for the port has been updated to a value greater than BURST_VAL. Maximizing the values of MAXBURST1 and MAXBURST2 gives the greatest time between credit update and potential decrement below BURST_VAL (which will eventually happen if enough SATISFIED status conditions occur). This in turn simplifies the design of a transmit FIFO data write state machine. 5. In order to ensure that a full BURST_VAL block of data is always available when a port is serviced, it is necessary to synchronize the writing of data to each port's transmit FIFO to the transmitter's FIFO read sequence. This can be done by monitoring the PORT_ID of the currently serviced SPI4 port (SPI[A,B]_k_PORT_ID). Figure 21, Figure 22, and Figure 23 show write sequencing that would result in sufficiently full transmit FIFOs for full data bursts at all times (except for end-of-packet) for 32-bit, 64-bit, and 128-bit aggregation modes respectively. The figures illustrate the most stringent polling sequencing that would still allow consistently full data bursts. For example, the minimum required gap between polls of the same port is determined by the aggregation mode chosen. Longer gaps between epeated port polling will result in more flexibility in timing the transmit FIFO writes. The examples in Figure 21, Figure 22, and Figure 23 illustrate a BURST_VAL of 4, but are extendable to BURST_VAL values from 2 to 15. Note that BURST_VAL for each port is available on SPI[A,B]_k_BURST_VAL. This may be useful in cases where BURST_VAL has not been set to the same value for each port.
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Lattice Semiconductor
Figure 21. Write Synchronization Sequence for 32-Bit Mode
Transmit Calendar Minimum Port Gap for 32-bit Mode
ORCA ORSPI4 Data Sheet
. .
Port 0 Set equal BURST_VAL for all ports Port 1 Port 2 Port 3 Port 0 Each port in a minimum separation must be located in a different bank Minimum separation between repeating port numbers in Transmit Calendar = 4 for 32-bit mode to allow time to load Transmit FIFOs for data bursts of any length
. . 32-bit Mode (BURST_VAL = 4 example)
SPI[A,B]_k_CLK_j
SPI[A,B]_k_PORT_ID
...
...
Port 0
Port 1
Port 2
Port 3
Port 0
...
1 port duration = BURST_VAL clock cycles
End of data burst read for Port 0
Port 0, write 1
Port 0, write 2
Port 0, write 3
Port 0, write 4
Range for Transmit FIFO writes
Start 1 st write no sooner than 6 clock cycles before beginning of initial port cycle*
* Rules valid for any value of BURST_VAL in 32-bit mode
End last write no later than 2 clock cycles before end of port cycle*
Conditions for writing to transmit FIFO: 1. If BURST_VAL worth of data is ready to be transmitted and 2. Port status is not SATISFIED and 3. Within valid time to load portis transmit FIFO as shown above then OK to load transmit FIFO with BURST_VAL of data for that port
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Lattice Semiconductor
Figure 22. Write Synchronization Sequence for 64-Bit Mode
Transmit Calendar Minimum Port Gap for 64-bit Mode
ORCA ORSPI4 Data Sheet
. .
Set equal BURST_VAL for all ports Port 0 Port 1 Port 0 Minimum separation between repeating port numbers in Transmit Calendar = 2 for 64-bit mode to allow time to load Transmit FIFOs for data bursts of any length Both ports in a minimum separation must be located in a different bank
. . 64-bit Mode (BURST_VAL = 4 example)
SPI[A,B]_k_CLK_j
SPI[A,B]_k_PORT_ID
...
...
Port 0
Port 1
Port 0
...
1 port duration = BURST_VAL clock cycles
End of data burst read for Port 0 Port 0, write 3 Port 0, write 4
Port 0, write 1
Port 0, write 2
Range for Transmit FIFO writes
Start 1 st write no sooner than 4 clock cycles before beginning of initial port cycle*
End last write no later than 2 clock cycles before end of port cycle*
* Rules valid for any value of BURST_VAL in 64-bit mode
Conditions for writing to transmit FIFO: 1. If BURST_VAL worth of data is ready to be transmitted and 2. Port status is not SATISFIED and 3. Within valid time to load portis transmit FIFO as shown above then OK to load transmit FIFO with BURST_VAL of data for that port
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Lattice Semiconductor
Figure 23. Write Synchronization Sequence for 128-Bit Mode
Transmit Calendar Minimum Port Gap for 128-bit Mode
ORCA ORSPI4 Data Sheet
. .
Port 0 Port 0 128-bit mode allows for consecutive port polling for any value of BURST_VAL
. . 128-bit Mode (BURST_VAL = 4 example)
SPI[A,B]_k_CLK_j
SPI[A,B]_k_PORT_ID
...
...
Port 0
Port 0
...
1 port duration = BURST_VAL clock cycles
End of data burst read for Port 0
Range for Transmit FIFO writes
Start 1 st write no sooner than 3 clock cycles before beginning of initial port cycle*
* Rules valid for any value of BURST_VAL in 128-bit mode
Conditions for writing to transmit FIFO: 1. If BURST_VAL worth of data is ready to be transmitted and 2. Port status is not SATISFIED and 3. Within valid time to load portis transmit FIFO as shown above then OK to load transmit FIFO with BURST_VAL of data for that port
62
Port 0, w rite 1 Port 0, w rite 2 Port 0, w rite 3 Port 0, w rite 4 End last write no later than 2 clock cycles before end of port cycle*
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
6. In order to avoid straddling packets during a data burst, it is necessary to track the location of an end-ofpacket(EOP) within a data burst to insert a dummy word whenever the EOP does not occur within the final 128-bit (16-byte) word of a data burst. If an EOP does not occur during the final 128-bit word of a data burst, then the user must insert a dummy word with the packet error indicator (SPI[A,B]_k_ERR_j) set to 1 and the end of packet indicator (SPI[A,B]_k_EOP_j) set to 0. During the dummy write, all byte enables (SPI[A,B]_k_BE_j) should be set to 1 and input data can be set to anything (don't care). Examples of the placement of the dummy write in relation to the EOP are shown in Figure 24, Figure 25, and Figure 26.
Figure 24. Dummy Write Requirement for MIN_BURST_MODE (128-Bit Mode)
128-bit
1
2
BURST_VAL = n
. . .
n-3
EOP
If EOP occurs in any write EXCEPT last write for a given BURST_VAL, must include 1 dummy write before terminating writes for the port
Dummy Write: n-2 DUMMY WRITE SPI[A,B]_TX128_ERR = 1 SPI[A,B]_TX128_EOP = 0 SPI[A,B]_TX128_BE[15:0] = 0xFFFF SPI[A,B]_TX128_DATA = Donit Care
n-1
n
EOP OK
If EOP occurs in last write as defined by the BURST_VAL, then no dummy write is required
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Lattice Semiconductor
Figure 25. Dummy Write Requirement for MIN_BURST_MODE (64-Bit Mode)
64-bit 64-bit
ORCA ORSPI4 Data Sheet
1
2 If EOP occurs in any write EXCEPT last two writes for a given BURST_VAL, must include 1 dummy write before terminating writes for the port
. . . EOP
BURST_VAL = n
Dummy Write: DUMMY WRITE SPI[A,B]_TX64_ERR_j = 1 SPI[A,B]_TX64_EOP_j = 0 SPI[A,B]_TX64_BE_j(7:0) = 0xFF SPI[A,B]_TX64_DATA = Donit Care
n-2
n-1 If EOP occurs in last two writes as defined by the BURST_VAL, then no dummy write is required
n
EOP OK
EOP OK
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Lattice Semiconductor
Figure 26. Dummy Write Requirement for MIN_BURST_MODE (32-Bit Mode)
32-bit 32-bit 32-bit 32-bit
ORCA ORSPI4 Data Sheet
1
2
BURST_VAL = n
. . .
EOP
If EOP occurs in any write EXCEPT last four writes for a given BURST_VAL, must include 1 dummy write before terminating writes for the port
Dummy Write: n-2
DUMMY WRITE
SPI[A,B]_TX32_ERR_j = 1 SPI[A,B]_TX32_EOP_j = 0 SPI[A,B]_TX32_BE_j(3:0) = 0xF SPI[A,B]_TX32_DATA = Donit Care
n-1
n
EOP OK
EOP OK
EOP OK
EOP OK
If EOP occurs in last four writes as defined by the BURST_VAL, then no dummy write is required
SPI4 FPGA/Embedded Core Timing Delays
When designing application logic within the FPGA to interface with the embedded core, it is important to consider the input setup and hold time requirements of the embedded core logic. There are two directions for signaling information between the FPGA and the embedded core. The first is where the FPGA sources transmit data and associated control signals into the embedded core. Data in this direction is always synchronous to the clock source within the FPGA. The other data path direction is used to convey Calendar port and status information from the embedded core to the FPGA. All signals in this category are synchronous to the buffered reference clock within the embedded core. All timing is handled in the ispLEVER software using frequency preferences on the associated clocks.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
FPGA Sourced Data and Control In this mode, the FPGA sends data into the embedded core relative to the rising edge of it's own clock as well as providing the clock for the embedded core. The embedded core uses the FPGA clock to register all input data and control signals. Figure 27 shows the Worst Case Slow and Worst Case Fast propagation delays for the FPGA input data and control signals as well as the clock signal. For guaranteed performance it is important that all input signals from the FPGA be registered before being sent into the embedded core.
Clocking Schemes and Timing Diagrams - Transmit DPRAM Interface
Figure 27. Data: SPI[A,B]_DATA/SOP/EOP/BE/ERR/PORT/WE/ADDR/SPI[A,B]_TXk_WD_CNT_RST /LINK_DIS Clock: SPI[A,B]_k_CLK_[3:0]; k=32, 64,128
4.81 / 1.18 ns 3.5/0.5 ns Q Buffer Delay D
Delay
D1
1.5/0.5 ns C Delay Setup = 2.6 ns Hold = - 0.32 ns 1.36/ 0.47 ns FPGA Embedded Core
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
Embedded Core Sourced Status The embedded core sources port and status information relative to a buffered version of the externally provided reference clock (TREFCLK). The FPGA receives both the status information and clock, and can use the provided clock to synchronize all status information for it's own use. Figure 28 shows the Worst Case Slow and Worst Case Fast propagation delays for the embedded core output status signals as well as the clock signal. With the given timing delays the FPGA logic can either immediately register the provided status information or, if required, implement some combinatorial logic function before registering the information.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Figure 28. Data: ATX_PORTID[7:0], BTX_PORTID[7:0], ATX_STAT[1:0], BTX_STAT[1:0], ABURST_VAL[3:0], BBURST_VAL[3:0] Clock: ATREFCLK, BTREFCLK
5.4 / 2.1 ns (includes ck to Q) Delay
Buffer 3.5/0.5 ns Delay D D
Q
D Clock Insertion Delay = 6.8 / 2.4 ns
ATREFCK_F BTREFCLK_F
Clock Buffer Delay 4.0/1.0 ns Relative to Data C
TREFCLK (from off-chip)
1.36/ 0.47 ns FPGA Embedded Core
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
SPI4 Transmit Software Interface
The SPI4 transmit interface is configurable through a System Bus interface incorporated within the embedded core. The user can gain access to the System Bus either through the integrated MPI interface, or through FPGA resources using the System Bus Master/Slave interface. Please refer to the appropriate Lattice Semiconductor data sheets and application notes for more information regarding these interfaces. The Transmit SPI4 interface logic incorporates many configurable control registers, as well as interrupt and status registers to monitor SPI4 performance. Table 47 provides a memory map and description of each register within the Transmit portion of the SPI4 embedded core.
Special Operating Modes
Quarter-Rate Mode The ORSPI4 SPI4 TX interface is designed to operate at data rates much lower than 622 Mbps. Even though the OIF standard specifies a minimum data rate of 622 Mbits/s, the lower data rates are provided for users who wish to use the SPI4 link for applications supporting <10 Gbits/s aggregate bandwidth (STS-48, STS-3, Gb Ethernet, etc.). To enable this low speed mode, user should set the software register bit SPI4_QUARTER_RATE (Address 30915 in SPIA and 30A15 in SPIB) to `1'. This supports data rates in the range of 100 - 200 Mbps. Note that the normal operating modes 32-bit, 64-bit and 128-bit are independent of the quarter-rate mode. In quarter-rate mode, the transmit PLL is held in reset by setting the MRESET hardware pin to `1'. The PLL bypass mode is enabled by setting the BYPASS pin to `1' which causes the SPI[A,B]_TREFCLK_X8 clock from the FPGA to be used as the transmit reference clock. It must be two- times the desired Transmit SPI4 line clock rate. When not operating the Transmit SPI4 core in quarter-rate mode, this signal should be tied off. Ex: For a 100 MHz Transmit SPI4 line clock, SPIA_TREFCLK_X8 from the FPGA must be 200 MHz.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
ORSPI4 SPI4 Receive Path Functional Description
This section describes the receive section of the SPI4 interface. Although there will be two SPI4 compliant interfaces within the FPSC, this section describes a single interface. The other interface is a duplicate and therefore needs no additional technical description. ORSPI4 Receive Features The Receive SPI4 interface supports the following features: * 10 Gbits/s data throughput. * Four dual-port memory banks supporting buffering for up to 32 ports. If support for more than 32 ports is needed, then the dual-port memories can be used for clock domain crossing purposes and data can be buffered in an external memory. * Port Status Sequencer (PSS), including Receive Calendar (main and shadow), will support up to 256 ports, the maximum number of ports supported by the SPI4 standard. * 32, 64 and 128-bit data width aggregation modes at the user (core/FPGA) interface. * Programmable main and shadow calendar table. All calendar configuration parameters specified in the SPI4 standard such as CALENDAR_LEN, CALENDAR_M are supported. * Optional dynamic alignment of receive data at the high-speed SPI4 interface. Dynamic alignment is required at rates > 700 Mbits/s (350 MHz). The SPI4 receive logic enables users to read incoming port data using a variety of interfaces and associated clock domain options. It uses Dual Port RAMs (DPRAM) for temporary storage and clock domain crossing. Data is received in SPI4 format as LVDS signals at the receive interface. The data is written into DPRAM as received and read from the DPRAMs as requested by the FPGA logic. FIFO status is transmitted from the Receive Status interface according to a pre-configured polling sequence contained within the Receive Calendar. Data is formatted into the SPI4 Receive Status format and sent to the physical links as either LVDS or LVTTL signals. There are also several other features incorporated into the embedded core such as parallel loopback and far end loopback to assist in debugging and statistic gathering. These features, and the SPI4 data formats and initialization procedures are documented in separate sections since they involve both the transmit and receive paths. The major blocks associated with the ORSPI4 receiver are: * SPI4 Receive Logic - Data - SPI4 Receive Data Input (RDI) block - SPI4 Receive Data Protocol (RDP) logic * Data Formatter * Address Map * DPRAM Banks * Port Status Sequencer Logic (PSS) * SPI4 Receive Logic - Status - SPI4 Receive Status Protocol (RSP) logic - SPI4 Receive Status Output (RSO) block
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ORCA ORSPI4 Data Sheet
These blocks will be described in detail in the following sections. The ORSPI4 Receive functional block diagram is shown in Figure 29.
Figure 29. ORSPI4 Receive Functional Block Diagram
SPI[A,B]_k_DATA_j, BE_j SPI[A,B]_k_ CTL_j (32 and 64 only) k = 32, 64 or 128 j= 0, 1, 2 or 3
FPGA Interface
SPI[A,B]_k_SOPj, EOPj, ERRj [A,B]STOP_ON_EOPj SPI[A,B]_k_RD_j SPI[A,B]_k_CLK_j SPI[A,B]_k_ADDR_j SPI[A,B]_k_FIFO_EMPTY_j
data
3
control RX DPRAM RDP
16
[A,B]RDAT [A,B]RCTL [A,B]RDCLK
data control
RDI
3
control
Address Mapper
[A,B]RLSCLK_F SPI[A,B]_k_STAT SPI[A,B]_k_PORT_ID SPI[A,B]_k_PSS_WE SPI[A,B]_k_PSS_CLK
2 8
RLSTAT
2
2
[A,B]RSTAT [A,B]RSCLK
SPI[A,B]_k_EXT_STAT_EN
PSS
RSP
RLSCLK
RSO
ORSPI4 Receive Functional Block Overview
The ORSPI4 high-speed receive logic receives high-speed data on 16 LVDS pairs (RDAT[15:0]), control on one LVDS pair (RCTL) and clock on one LVDS pair (RDCLK) at the SPI4 interface. This is an OIF-SPI-4 02.0 compliant interface that supports data rates in the range of 622-900 Mbps. Additionally lower-speed data in the range of 100200 Mbps is also supported. The high-speed receive interface logic supports both static and dynamic alignment as specified by the OIF-SPI-4 02.0 specification. Dynamic alignment allows for +/- one bit period of skew. During dynamic alignment, training patterns are detected and deskew performed. Data is then deserialized into 128-bit data and 8-bit control bus. The SPI4 receive data protocol logic then extracts the control information such as PORT_ID, SOP, EOP and ERR into a separate sideband bus while still preserving wire-speed throughput. Data and control signals are then written into one of four dual-port RAMs (DPRAMs). Per-port buffering is supported for a maximum of 32 ports. The DPRAMs are built as multiple virtual FIFOs where each FIFO can be allocated for a port by the user through software. At the FPGA fabric, the user reads data for the desired ports from the FIFOs
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ORCA ORSPI4 Data Sheet
based on the empty status signals presented from the FIFOs. The user can select a 32-bit, 64-bit or 128-bit wide FIFO interface depending on the FPGA design requirements. There are two SPI4 cores in the ORSPI4 device. They are referenced in the document as SPIA and SPIB respectively.
ORSPI4 Receive Embedded Core/FPGA Interface Description
ORSPI4 Receive I/O Modes The FPGA interface I/Os to the ORSPI4 logic block vary depending on the operating modes. There are three main user operating modes: * 32-bit operating mode: Each of the four DPRAMs can be configured with a 32-bit user data plus controls across the FPGA interface. This mode is particularly useful if the user is aggregating multiple 32-bit interfaces into a single SPI4 interface. * 64-bit operating mode: A DPRAM pair can be configured with 64-bit user data bus plus controls across the FPGA interface. Two such DPRAM pairs are available. More flexibility is provided by configuring one pair of DPRAM banks in 64-bit mode and the remaining two banks in 32-bit mode. * 128-bit operating mode: All four DPRAM banks are aggregated into a single FIFO with a 128-bit user data interface. Several other features are: * Ability to pause for two clock cycles when an EOP is detected using the ASTOP_ON_EOP (SPIA) or BSTOP_ON_EOP (SPIB) control signal. Please refer to the timing diagrams for detailed information. Table 12 lists I/Os for SPIA core only. They are identical in the SPIB core as well.
Table 12. SPIA Core Receive FPGA Interface in 32-Bit Mode
DPRAM FPGA Interface I/Os SPIA_RX32_ADDR_0[2:0] SPIA_RX32_DATA_0[31:0] SPIA_RX32_BE_0[3:0] Direction From/To FPGA Core FIFO read address. Core FPGA FIFO read data. Core FPGA Byte enables Bit 3 - Byte enable for SPIA_RX32_DATA_0[31:24] Bit 2 - Byte enable for SPIA_RX32_DATA_0[23:16] Bit 1 - Byte enable for SPIA_RX32_DATA_0[15:8] Bit 0 - Byte enable for SPIA_RX32_DATA_0[7:0] Core FPGA Port ID indicator. A `1' indicates that the SPIA_RX32_DATA_0 bus contains the port ID. Core FPGA Start of Packet Indicator. A `1' indicates start of packet. Core FPGA End of Packet Indicator. A `1' indicates end of packet. Core FPGA Error. A `1' indicates an error in the current word. Description
SPIA_RX32_CTL_0 SPIA_RX32_SOP_0 0 SPIA_RX32_EOP_0 SPIA_RX32_ERR_0
SPIA_RX32_FIFO_EMPTY_0 Core FPGA FIFO Empty flag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0] software register bit in address 0x30920. When this bit is set to `0', (default) the empty flag indicates truly empty. When this bit is set to `1', the empty flag indicates that the FIFO is 1/4 full 1. ASTOP_ON_EOP0 SPIA_RX32_CLK_0 SPIA_RX32_RD_0 FPGA Core Timing control for handling end of packet. FPGA Core FIFO read clock. FPGA Core FIFO read enable.
Note: For SPIB replace A with B
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Table 12. SPIA Core Receive FPGA Interface in 32-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_RX32_ADDR_1[2:0] SPIA_RX32_DATA_1[31:0] SPIA_RX32_BE_1[3:0] Direction From/To FPGA Core FIFO read address. Core FPGA FIFO read data.
ORCA ORSPI4 Data Sheet
Description
Core FPGA Byte enables Bit 3 - Byte enable for SPIA_RX32_DATA_1[31:24] Bit 2 - Byte enable for SPIA_RX32_DATA_1[23:16] Bit 1 - Byte enable for SPIA_RX32_DATA_1[15:8] Bit 0 - Byte enable for SPIA_RX32_DATA_1[7:0] Core FPGA Port ID indicator. A `1' indicates that the SPIA_RX32_DATA_1 bus contains the port ID. Core FPGA Start of Packet Indicator. A `1' indicates start of packet. Core FPGA End of Packet Indicator. A `1' indicates end of packet. Core FPGA Error. A `1' indicates an error in the current word.
SPIA_RX32_CTL_1 1 SPIA_RX32_SOP_1 SPIA_RX32_EOP_1 SPIA_RX32_ERR_1
SPIA_RX32_FIFO_EMPTY_1 Core FPGA FIFO Empty flag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[1] software register bit in address 0x30920. When this bit is set to `0', (default) the empty flag indicates truly empty. When this bit is set to `1', the empty flag indicates that the FIFO is 1/4 full -1. ASTOP_ON_EOP1 SPIA_RX32_CLK_1 SPIA_RX32_RD_1 SPIA_RX32_ADDR_2[2:0] SPIA_RX32_DATA_2[31:0] SPIA_RX32_BE_2[3:0] FPGA Core Timing control for handling end of packet. FPGA Core FIFO read clock. FPGA Core FIFO read enable. FPGA Core FIFO read address. Core FPGA FIFO read data. Core FPGA Byte enables Bit 3 - Byte enable for SPIA_RX32_DATA_2[31:24] Bit 2 - Byte enable for SPIA_RX32_DATA_2[23:16] Bit 1 - Byte enable for SPIA_RX32_DATA_2[15:8] Bit 0 - Byte enable for SPIA_RX32_DATA_2[7:0] Core FPGA Port ID indicator. A `1' indicates that the SPIA_RX32_DATA_2 bus contains the port ID. Core FPGA Start of Packet Indicator. A `1' indicates start of packet. Core FPGA End of Packet Indicator. A `1' indicates end of packet. Core FPGA Error. A `1' indicates an error in the current word.
SPIA_RX32_CTL_2 2 SPIA_RX32_SOP_2 SPIA_RX32_EOP_2 SPIA_RX32_ERR_2
SPIA_RX32_FIFO_EMPTY_2 Core FPGA FIFO Empty flag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[2] software register bit in address 0x30920. When this bit is set to `0', (default) the empty flag indicates truly empty. When this bit is set to `1', the empty flag indicates that the FIFO is 1/4 full -1. ASTOP_ON_EOP2 SPIA_RX32_CLK_2 SPIA_RX32_RD_2 FPGA Core Timing control for handling end of packet. FPGA Core FIFO read clock. FPGA Core FIFO read enable.
Note: For SPIB replace A with B
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Table 12. SPIA Core Receive FPGA Interface in 32-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_RX32_ADDR_3[2:0] SPIA_RX32_DATA_3[31:0] SPIA_RX32_BE_3[3:0] Direction From/To FPGA Core FIFO read address. Core FPGA FIFO read data.
ORCA ORSPI4 Data Sheet
Description
Core FPGA Byte enables Bit 3 - Byte enable for SPIA_RX32_DATA_3[31:24] Bit 2 - Byte enable for SPIA_RX32_DATA_3[23:16] Bit 1 - Byte enable for SPIA_RX32_DATA_3[15:8] Bit 0 - Byte enable for SPIA_RX32_DATA_3[7:0] Core FPGA Port ID indicator. A `1' indicates that the SPIA_RX32_DATA_3 bus contains the port ID. Core FPGA Start of Packet Indicator. A `1' indicates start of packet. Core FPGA End of Packet Indicator. A `1' indicates end of packet. Core FPGA Error. A `1' indicates an error in the current word.
SPIA_RX32_CTL_3 3 SPIA_RX32_SOP_3 SPIA_RX32_EOP_3 SPIA_RX32_ERR_3
SPIA_RX32_FIFO_EMPTY_3 Core FPGA FIFO Empty flag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[3] software register bit in address 0x30920. When this bit is set to `0', (default) the empty flag indicates truly empty. When this bit is set to `1', the empty flag indicates that the FIFO is 1/4 full -1. ASTOP_ON_EOP3 SPIA_RX32_CLK_3 SPIA_RX32_RD_3 SPIA_RX32_PORT_ID[7:0] SPIA_RX32_STAT[1:0] Status SPIA_RX32_EXT_STAT_EN I/Os SPIA_RX32_PSS_WE SPIA_RX32_PSS_CLK SPI_DATM_A Misc. I/Os FPGA Core Timing control for handling end of packet. FPGA Core FIFO read clock. FPGA Core FIFO read enable. FPGA Core Port ID used by the core as write address into the status RAM. FPGA Core Port Status corresponding to SPIA_RX32_PORT_ID FPGA Core When set to `1', the status from SPIA_RX32_STAT will be sent on the SPI4 status i/f. FPGA Core Write enable to the internal Status RAM. FPGA Core Write clock to the internal Status RAM. FPGA Core Valid only during static data capture. Should be set to `0' in dynamic alignment mode. `0' - Bypass delay line circuit on the clock (ARDCLK) path. `1' - Enables delay line circuit on the ARDCLK path. FPGA Core These bits control the effective delay of the delay line circuit on the ARDCLK path. Valid values are from 0-6. Core FPGA Internal clock (ARDCLK/4) used to clock all receive status logic.
SPI_DLYTAP_A[2:0] ARLSCLK_F
Note: For SPIB replace A with B
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ORCA ORSPI4 Data Sheet
Table 13. SPIA Core Receive FPGA Interface in 64-Bit Mode
DPRAM FPGA Interface I/Os SPIA_RX64_ADDR_0[2:0] SPIA_RX64_DATA_0[63:0] SPIA_RX64_BE_0[7:0] Direction From/To FPGA Core FIFO read address. Core FPGA FIFO read data. Core FPGA Byte enables Bit 7 - Byte enable for SPIA_RX64_DATA_0[63:56] Bit 6 - Byte enable for SPIA_RX64_DATA_0[55:48] Bit 5 - Byte enable for SPIA_RX64_DATA_0[47:40] Bit 4 - Byte enable for SPIA_RX64_DATA_0[39:32] Bit 3 - Byte enable for SPIA_RX64_DATA_0[31:24] Bit 2 - Byte enable for SPIA_RX64_DATA_0[23:16] Bit 1 - Byte enable for SPIA_RX64_DATA_0[15:8] Bit 0 - Byte enable for SPIA_RX64_DATA_0[7:0] Core FPGA Port ID indicator. A `1' indicates that the SPIA_RX64_DATA_0 bus contains the port ID. Core FPGA Start of Packet Indicator. A `1' indicates start of packet. Core FPGA End of Packet Indicator. A `1' indicates end of packet. Core FPGA Error. A `1' indicates an error in the current word. Description
0
SPIA_RX64_CTL_0 SPIA_RX64_SOP_0 SPIA_RX64_EOP_0 SPIA_RX64_ERR_0
SPIA_RX64_FIFO_EMPTY_0 Core FPGA FIFO Empty flag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0] software register bit in address 0x30920. When this bit is set to `0', (default) the empty flag indicates truly empty. When this bit is set to `1', the empty flag indicates that the FIFO is 1/4 full -1. ASTOP_ON_EOP0 SPIA_RX64_CLK_0 SPIA_RX64_RD_0 SPIA_RX64_ADDR_1[2:0] SPIA_RX64_DATA_1[63:0] SPIA_RX64_BE_1[7:0] FPGA Core Timing control for handling end of packet. FPGA Core FIFO read clock. FPGA Core FIFO read enable. FPGA Core FIFO read address. Core FPGA FIFO read data. Core FPGA Byte enables Bit 7 - Byte enable for SPIA_RX64_DATA_1[63:56] Bit 6 - Byte enable for SPIA_RX64_DATA_1[55:48] Bit 5 - Byte enable for SPIA_RX64_DATA_1[47:40] Bit 4 - Byte enable for SPIA_RX64_DATA_1[39:32] Bit 3 - Byte enable for SPIA_RX64_DATA_1[31:24] Bit 2 - Byte enable for SPIA_RX64_DATA_1[23:16] Bit 1 - Byte enable for SPIA_RX64_DATA_1[15:8] Bit 0 - Byte enable for SPIA_RX64_DATA_1[7:0] Core FPGA Port ID indicator. A `1' indicates that the SPIA_RX64_DATA_1 bus contains the port ID. Core FPGA Start of Packet Indicator. A `1' indicates start of packet. Core FPGA End of Packet Indicator. A `1' indicates end of packet. Core FPGA Error. A `1' indicates an error in the current word.
1
SPIA_RX64_CTL_1 SPIA_RX64_SOP_1 SPIA_RX64_EOP_1 SPIA_RX64_ERR_1
SPIA_RX64_FIFO_EMPTY_1 Core FPGA FIFO Empty flag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0] software register bit in address 0x30920. When this bit is set to `0', (default) the empty flag indicates truly empty. When this bit is set to `1', the empty flag indicates that the FIFO is 1/4 full -1. ASTOP_ON_EOP1 SPIA_RX64_CLK_1 SPIA_RX64_RD_1 FPGA Core Timing control for handling end of packet. FPGA Core FIFO read clock. FPGA Core FIFO read enable.
Note: For SPIB replace A with B
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Table 13. SPIA Core Receive FPGA Interface in 64-Bit Mode (Continued)
DPRAM FPGA Interface I/Os SPIA_RX64_PORT_ID[7:0] SPIA_RX64_STAT[1:0] Status SPIA_RX64_EXT_STAT_EN I/Os SPIA_RX64_PSS_WE SPIA_RX64_PSS_CLK SPI_DATM_A Misc. I/Os Direction From/To
ORCA ORSPI4 Data Sheet
Description
FPGA Core Port ID used by the core as write address into the status RAM. FPGA Core Port Status corresponding to SPIA_RX64_PORT_ID FPGA Core When set to `1', the status from SPIA_RX64_STAT will be sent on the SPI4 status i/f. FPGA Core Write enable to the internal Status RAM. FPGA Core Write clock to the internal Status RAM. FPGA Core Valid only during static data capture. Should be set to `0' in dynamic alignment mode. `0' - Bypass delay line circuit on the clock (ARDCLK) path. `1' - Enables delay line circuit on the ARDCLK path. FPGA Core These bits control the effective delay of the delay line circuit on the ARDCLK path. Valid values are from 0-6. Core FPGA Internal clock (ARDCLK/4) used to clock all receive status logic.
SPI_DLYTAP_A[2:0] ARLSCLK_F
Note: For SPIB replace A with B
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ORCA ORSPI4 Data Sheet
Table 14. SPIA Core Receive FPGA Interface in 128-Bit Mode
DPRAM FPGA Interface I/Os SPIA_RX128_ADDR[2:0] SPIA_RX128_DATA[127:0] SPIA_RX128_BE[15:0] Direction From/To FPGA Core FIFO read address. Core FPGA FIFO read data. Core FPGA Byte enables Bit 15- Byte enable for SPIA_RX128_DATA[127:120] Bit 14- Byte enable for SPIA_RX128_DATA[119:112] Bit 13- Byte enable for SPIA_RX128_DATA[111:104] Bit 12- Byte enable for SPIA_RX128_DATA[103:96] Bit 11- Byte enable for SPIA_RX128_DATA[95:88] Bit 10- Byte enable for SPIA_RX128_DATA[87:80] Bit 9- Byte enable for SPIA_RX128_DATA[79:72] Bit 8- Byte enable for SPIA_RX128_DATA[71:64] Bit 7 - Byte enable for SPIA_RX128_DATA[63:56] Bit 6 - Byte enable for SPIA_RX128_DATA[55:48] Bit 5 - Byte enable for SPIA_RX128_DATA[47:40] Bit 4 - Byte enable for SPIA_RX128_DATA[39:32] Bit 3 - Byte enable for SPIA_RX128_DATA[31:24] Bit 2 - Byte enable for SPIA_RX128_DATA[23:16] Bit 1 - Byte enable for SPIA_RX128_DATA[15:8] Bit 0 - Byte enable for SPIA_RX128_DATA[7:0] Core FPGA Port ID for the current data. Core FPGA Start of Packet Indicator. A `1' indicates start of packet. Core FPGA End of Packet Indicator. A `1' indicates end of packet. Core FPGA Error. A `1' indicates an error in the current word. Core FPGA FIFO Empty flag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0] software register bit in address 0x30920. When this bit is set to `0', (default) the empty flag indicates truly empty. When this bit is set to `1', the empty flag indicates that the FIFO is 1/4 full -1. FPGA Core Timing control for handling end of packet. FPGA Core FIFO read clock. FPGA Core FIFO read enable. FPGA Core Port ID used by the core as write address into the status RAM. FPGA Core Port Status corresponding to SPIA_RX128_PORT_ID Description
0
SPIA_RX128_PORTID[7:0] SPIA_RX128_SOP SPIA_RX128_EOP SPIA_RX128_ERR SPIA_RX128_FIFO_EMPTY
ASTOP_ON_EOP SPIA_RX128_CLK SPIA_RX128_RD SPIA_RX128_PORT_ID[7:0] SPIA_RX128_STAT[1:0]
SPIA_RX128_EXT_STAT_EN FPGA Core When set to `1', the status from SPIA_RX128_STAT will be sent on the SPI4 status i/f. SPIA_RX128_PSS_WE SPIA_RX128_PSS_CLK SPI_DATM_A Misc. I/Os FPGA Core Write enable to the internal Status RAM. FPGA Core Write clock to the internal Status RAM. FPGA Core Valid only during static data capture. Should be set to `0' in dynamic alignment mode. `0' - Bypass delay line circuit on the clock (ARDCLK) path. `1' - Enables delay line circuit on the ARDCLK path. FPGA Core These bits control the effective delay of the delay line circuit on the ARDCLK path. Valid values are from 0-6. Core FPGA Internal clock (ARDCLK/4) used to clock all receive status logic.
SPI_DLYTAP_A[2:0] ARLSCLK_F
Note: For SPIB replace A with B
SPI4 Receive Logic Blocks - Detailed Description
RDI Block The SPI4 high-speed Receive Data Input (RDI) block contains the high-speed receive logic for the SPI4 block. Incoming LVDS signals, in SPI4 format, include the 16-bit data bus (RDAT[15:0]), a control bit (RCTL) and a source
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ORCA ORSPI4 Data Sheet
synchronous DDR clock (RDCLK). The 16-bit data bus and control signal are DDR with respect to RDCLK. The incoming data is deserialized to a 128-bit format and the control information is converted to an 8-bit format. Deserialized data, control signals and a low-speed clock, derived from the high-speed RDCLK, are forwarded to the protocol (RDP) block. The RDI block alignment logic detects training patterns and perform dynamic alignment of the incoming data. For low speed incoming data at rates up to 700 Mbits/s, static alignment can be chosen through a programmable control bit. The low speed mode is described in a later section. At speeds above 700 Mb/s (350 MHz), however, it becomes necessary to use dynamic alignment. Skews of up to one clock period can be compensated for by the dynamic alignment logic, which chooses the best phase of the receive clock, out of 16 possibilities, to center each data bit for the best possible setup/hold margin. The receive dynamic alignment logic periodically samples the data to verify that data can be transferred reliably as temperature and voltage levels in the system vary. It then makes appropriate adjustments as needed. The output from the RDI block is the low speed 128-bit data bus and 8-bit control bus along with a low speed clock which is 1/4th the rate of the SPI4 receive clock RDCLK. The ORSPI4 receive high-speed interface also supports static data capture as shown in Figure 30. As shown in the figure, the key difference that exists between the clock and data paths is the delay line in the clock path. The highspeed loopback works in both static and dynamic alignment modes. The delay line circuit is a series of buffers with programmable stages that are controlled through two signals from the FPGA - SPI_DATM_A (SPIA) or SPI_DATM_B (SPIB) and SPI_DLYTAP_A[2:0] (SPIA) or SPI_DLYTAP_B[2:0] (SPIB). The object of having programmable delay stages is to delay RDCLK appropriately so that both its rising and falling edges hit the data eye with sufficient setup and hold margin for data capture. Various delay settings allow the data to be centered vs. the clock for the best setup and hold margin. For details on programming the ORSPI4 receiver in static and dynamic capture modes, refer to the section "Static Capture Operating Mode".
Figure 30. Static Data Capture
[A,B]RDAT[15:0] LVDS Buffers
0 1
data
Dynamic
clock
SPI4_LOOPBK_HS
[A,B]RDCLK
LVDS Buffers
0 1
Delay Line
data clock
Static
SPI_DLYTAP_[A,B][2:0]
From Transmit Blocks
SPI_DATM_[A,B]
(Controls from FPGA)
RDP Block The SPI4 Receive Data Protocol (RDP) block receives data from RDI block and is responsible for decoding the inband control information while preserving wire-speed throughput. It passes both data and control information, such as link address, SOP, EOP and error, to the Receive DPRAMs. The RDP block also parses the control words embedded within the incoming data. Using this control information, it performs the following functions: * Checks DIP-4 parity
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ORCA ORSPI4 Data Sheet
* Monitors for continuous alignment (if more than a programmable number of DIP-4 parity errors exist, there may be an alignment problem). In the event of DIP-4 parity errors, instructs the status block to send status framing pattern "11" on the receive SPI4 status bus. * Removes idle/training words. * Extracts link address and SOP, EOP and valid packet (no error) signals. Receive DPRAMs There are four DPRAMs referred to as banks 0, 1, 2 and 3. Each bank has a 32-bit data interface to the FPGA. Each DPRAM has its own individual read enable and read clock allowing it to be read by the FPGA application independently. Every DPRAM bank is configured by software to operate in one of 32-bit, 64-bit or 128-bit mode. Every DPRAM bank is also configured to contain 1, 2, 4 or 8 virtual FIFOs. The user determines the number of FIFOs depending on the number of ports and buffer requirements for the ports as required by a given application. The programming of a DPRAM bank in 32-bit, 64-bit or 128-bit mode and programming of the number of virtual FIFOs within a DPRAM bank is done through software as shown in Table 18. Note that in 64-bit mode, DPRAMs 0 and 1 have to be configured identically. The combined DPRAM pair is referred to as DPRAM "0". Similarly DPRAM pairs 2 and 3 have to be configured identically. This combined DPRAM pair is referred to as DPRAM "2". In 128-bit mode, all DPRAMs have to be configured identically. The combined DPRAM banks are collectively referred to as DPRAM "0". The aggregation modes can be used in five possible combinations as shown in Table 16. The size of the embedded data and control FIFOs for each mode is shown in Table 17. The user accesses a virtual FIFO using the 3-bit FIFO read address (refer to Table 12, Table 13, and Table 14) from the FPGA. Table 15 shows the indexed partition based upon the configured DPRAM partitioning and aggregation mode. In 32-bit operating mode, the user always reads data as four 32-bit word bursts (plus one additional clock cycle to read the port ID) unless an EOP is received. If an EOP occurs and the ASTOP_ON_EOPj (j=0,1,2,3) or BSTOP_ON_EOPj is `0', the core will cease transmission of the remaining words in the burst and start transferring the next set of data. For example, if the EOP happens in the second word of a 4-word burst, the core will not provide the remaining two words. Instead, it will start bursting the next set of data. The exception is when the ASTOP_ON_EOPj (j=0,1,2,3) or BSTOP_ON_EOPj is asserted. When this signal is `1', the core will pause for 2 clock cycles after an EOP. The byte enables (SPIA_RX32_BE_j) are set to `0' indicating that the read data is not valid.
Table 15. FIFO Address Based on Programmed Virtual FIFOs
FIFO Address (from FPGA) XXX 000 001 010 011 100 101 110 111 Description Ignored when a DPRAM is configured to support only one virtual FIFO Selects FIFO 0 when DPRAM is configured to support 2, 4 or 8 virtual FIFOs Selects FIFO 1 when DPRAM is configured to support 2, 4 or 8 virtual FIFOs Selects FIFO 2 when DPRAM is configured to support 4 or 8 virtual FIFOs Selects FIFO 3 when DPRAM is configured to support 4 or 8 virtual FIFOs Selects FIFO 4 when DPRAM is configured to support 8 virtual FIFOs Selects FIFO 5 when DPRAM is configured to support 8 virtual FIFOs Selects FIFO 6 when DPRAM is configured to support 8 virtual FIFOs Selects FIFO 7 when DPRAM is configured to support 8 virtual FIFOs
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Table 16. Possible Combinations of Aggregation Modes
Mode Banks 0 to 3 in 32-bit aggregation mode Banks 0, 1 in 64-bit aggregation mode, Banks 2,3 in 64-bit mode Banks 0,1 in 64-bit mode, Banks 2 & 3 in 32-bit mode Banks 0,1 in 32-bit mode, Banks 2 & 3 in 64-bit mode All banks in 128-bit Bank 0 in 32-bit mode, Bank 1 in 64-bit mode or vice-versa Bank 2 in 32-bit mode, Bank 3 in 64-bit mode or vice-versa Valid Yes Yes Yes Yes Yes No No
ORCA ORSPI4 Data Sheet
Table 17. Memory Size for Each Aggregation Mode and Partitioning
Number of Configured Virtual FIFO Partitions 1 32-bit 2 4 8 1 64-bit 2 4 8 1 128-bit 2 4 8
Operating Mode
DATA FIFO Depth (in Bytes) 2K 1K 512 256 4K 2K 1K 512 8K 4K 2K 1K
Control FIFO Depth (in Bytes) 512 256 128 64 1K 512 256 128 2K 1K 512 256
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Lattice Semiconductor
Table 18. Register Bit Settings for Aggregation Mode and Partition Size
DPRAM Aggregation Mode Address 30907 (SPIA), 30A07 (SPIB) DPRAM 0 (Register Bits 0:1) = 00 Virtual FIFO Partition Size Address 30906 (SPIA), 30A06 (SPIB) Register Bits 0:1 = 00 01 10 11 00 01 01 10 11 00 10 01 10 11 Register Bits 2:3 = 00 DPRAM 1 (Register Bits 2:3) = 00 01 10 11 00 01 01 10 11 00 10 01 10 11 Register Bits 4:5 = 00 DPRAM 2 (Register Bits 4:5) = 00 01 10 11 00 01 01 10 11
ORCA ORSPI4 Data Sheet
Configuration 32-bit data width, partition size 1 32-bit data width, partition size 2 32-bit data width, partition size 4 32-bit data width, partition size 8 64-bit data width, partition size 1 64-bit data width, partition size 2 64-bit data width, partition size 4 64-bit data width, partition size 8 128-bit data width, partition size 1 128-bit data width, partition size 2 128-bit data width, partition size 4 128-bit data width, partition size 8 32-bit data width, partition size 1 32-bit data width, partition size 2 32-bit data width, partition size 4 32-bit data width, partition size 8 64-bit data width, partition size 1 64-bit data width, partition size 2 64-bit data width, partition size 4 64-bit data width, partition size 8 128-bit data width, partition size 1 128-bit data width, partition size 2 128-bit data width, partition size 4 128-bit data width, partition size 8 32-bit data width, partition size 1 32-bit data width, partition size 2 32-bit data width, partition size 4 32-bit data width, partition size 8 64-bit data width, partition size 1 64-bit data width, partition size 2 64-bit data width, partition size 4 64-bit data width, partition size 8
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DPRAM Aggregation Mode Address 30907 (SPIA), 30A07 (SPIB)
ORCA ORSPI4 Data Sheet
Virtual FIFO Partition Size Address 30906 (SPIA), 30A06 (SPIB) 00 01 10 11 Register Bits 6:7 = 00
Configuration 128-bit data width, partition size 1 128-bit data width, partition size 2 128-bit data width, partition size 4 128-bit data width, partition size 8 32-bit data width, partition size 1 32-bit data width, partition size 2 32-bit data width, partition size 4 32-bit data width, partition size 8 64-bit data width, partition size 1 64-bit data width, partition size 2 64-bit data width, partition size 4 64-bit data width, partition size 8 128-bit data width, partition size 1 128-bit data width, partition size 2 128-bit data width, partition size 4 128-bit data width, partition size 8
10
DPRAM 3 (Register Bits 6:7) = 00
01 10 11 00 01 10 11 00 01 10 11
01
10
Receive Address Mapper This control block decodes the port address received from the SPI4 RX interface to determine the physical memory address (to access the DPRAM memories) for that port address. Each port address must be mapped to one of the virtual FIFOs in the DPRAMs. Each virtual FIFO can be used to buffer data for a single port. Since there is a total of four DPRAMs, eight virtual FIFOs in each DPRAM provides 32 per-port buffers. The number of per-port buffers varies according to the operating mode. For example, in 32-bit mode, a total of 32 per-port buffers is possible. In 64-bit mode, a total of 16 per-port buffers is provided. In 128-bit mode, a total of eight per-port buffers is provided. To decode the physical memory information, this block accesses a user-configured Port Descriptor Memory (PDM) which is simply a look-up-table. The PDM is an embedded memory within the ORSPI4 core. There is one each for SPIA and SPIB cores. Since 256 ports can be supported by the device, the PDM has 256 locations. The user indexes this memory using the 8-bit SPI4 Port ID as the software write address into the embedded memory space 31000 - 310FF. For example, a software write into address 31000 configures the PDM for port ID 0. The software procedure to configure the PDM is described below: * User has to select the PDM by writing a `1' into bit 3 of address 30917 (SPIA) or 30A17 (SPIB). * Subsequent writes to addresses 31000-310FF correspond to entries 0x00-0xFF in the PDM. These may be written in any order. * Upon completion of the PDM configuration, the PDM select bit (bit 3 of address 30917 or 30A17) must be set to `0'. * The contents of the PDM may also be read back. This is done by first selecting the PDM memory by writing a `1' to bit 3 of address 30917 or 30A17. Reads are then done from addresses 31000-310FF. Upon completion of the reads, the PDM select bit is set to `0'. To allocate a buffer space to a port, the user has to choose one of the four DPRAM banks (BANK_ID field in the PDM) and a virtual FIFO (PARTITION_ID) within the chosen DPRAM bank. Each location in the PDM contains the fields described below for each port address.
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ORCA ORSPI4 Data Sheet
Partition Address (PA): This is the least significant 3-bit field [2:0] within a PDM location. This field provides the virtual FIFO partition address for each port. Each partition is of equal size. There can be a total of 8 virtual FIFO partitions within each DPRAM bank. BANK_ID: This occupies bits 4:3 within a PDM location. This 2-bit field is used to select one of the four DPRAM banks to store the received data. The user initially assigns this information by programming the BANK_ID. Legal values for the BANK_ID depend on the operating mode. In 32-bit mode, the legal values are 0,1,2 and 3. In 64-bit mode, the legal values are 0 and 2. In 64-bit mode, the legal value is only 0. While programming the PDM allocates a buffer for every port (or multiple ports), the buffer sizes themselves are configured by the user through software register settings for * DPRAM aggregation mode (Address 30907 for SPIA and 30A07 for SPIB. Refer to Table 18) * Number of virtual FIFOs in a DPRAM (Address 30906 for SPIA and 30A06 for SPIB. Refer to Table 17). Figure 31 shows a block diagram of the Port Description Memory.
Figure 31. Receive Address Mapper Block Diagram
Software Write
Port Descriptor Memory
0
255
BANK_ID
PA
PDM Fields
Virtual Receive Memory FIFOs (Partitions) and Port Mapping As was the case for the transmit logic, there are up to 32 virtual receive FIFO partitioning, 256 port numbers and the receive calendar can contain up to 1023 entries. The user must set up the mapping between the FIFO partitions and the port number for each active port. The user must also set up the calendar sequence for polling the active ports. The simplest mapping of the read DPRAM partitions, which support a maximum of 32 ports, is to have a 1:1 mapping between the FIFO partition and the port address. The 1023 depth of the calendar allows for uneven bandwidth allocation across ports where high bandwidth ports can have multiple entries within the calendar table. The read scheduling logic, however, is designed to support up to 256 ports. Each port (up to 32 ports) can have its unique buffer. A single port or multiple ports can be assigned to a buffer by configuring the PDM. The user must, using FPGA logic, assure that data is read from the virtual FIFO using the same port sequencing that is expected
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ORCA ORSPI4 Data Sheet
by the calendar. This ensures that the bandwidth allocated for a given port is maintained and the port's FIFO is emptied at the same rate that it is being filled up at the far-end transmitter. For example, if the calendar assumes that the buffer for port 2 is filled more frequently than the buffer for port 4, then the FPGA logic must read the buffer (virtual FIFO) for port 2 more frequently than port 4 to ensure that bandwidth requested for port 2 is maintained across the SPI4 link. The user also has a choice to not use the per-port buffers and treat the DPRAMs as pure clock-domain crossing FIFOs. This is done by simply configuring each DPRAM in 128-bit mode and setting up the number of virtual FIFO partitions to "1". If the user application supports more than 32 ports, multiple ports need to share a buffer or external memory can be used. The ORSPI4 core provides a QDR-II SRAM Memory Controller for additional buffering. The QDR-II SRAM memory was chosen owing to the wire-speed throughput that can be realized through dedicated write and read ports. In this case, the user must implement control logic to sequence external memory reads from the selected virtual FIFOs and the FIFOs are used only for crossing between clock domains. In many cases a second QDR-II memory interface is needed, thus a soft IP version of the core is available. Suppose there are 6 ports, and each port is mapped to a single buffer or virtual FIFO: * The first step is to decide the aggregation mode and FIFO size depending on the bandwidth needed by the port(s). This is shown in Table 19. * The second step is to configure the DPRAMs through software register settings shown in Table 20. Note that DPRAM banks 2 and 3 are configured identically since they are configured to be a 64-bit interface. * The last step is to configure the PDM using the procedure described in the Address Mapper section. The contents of the PDM are shown in Table 21.
Table 19. DPRAM Configuration Example
DPRAM bank 0 1 2,3 Aggregation Mode 32-bit 32-bit 64-bit Number of Virtual FIFOs 2 2 2 Virtual FIFO Size (bytes) 1K 1K 2K
Table 20. DPRAM Software Register Settings Example
DPRAM Bank 0 1 2 3 Aggregation Mode RX_DPRAM_0_AGGR_MODE = 00 RX_DPRAM_1_AGGR_MODE = 00 RX_DPRAM_2_AGGR_MODE = 01 RX_DPRAM_3_AGGR_MODE = 01 Number of Virtual FIFOs RX_DPRAM_0_NUMFIFO = 01 RX_DPRAM_0_NUMFIFO = 01 RX_DPRAM_0_NUMFIFO = 01 RX_DPRAM_0_NUMFIFO = 01
Table 21. PDM Contents Example
Port ID 0x00 0x01 0x02 0x03 0x04 0x05 10 01 Bank ID 00 Partition Address 000 001 000 001 000 001
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ORCA ORSPI4 Data Sheet
Port Status Sequencer (PSS) Logic In addition to formatting received data and sending it to the FPGA logic, the receive block also sends status information to the SPI4 status interface. The Port Status Sequencer (PSS) block is responsible for providing port status to the SPI4 Receive Status Protocol block (RSP) according to a pre-configured calendar sequence. Status is derived from the fill-levels of the DPRAM FIFOs and/or from the FPGA status interface. When status is provided by FPGA logic, the FPGA application writes status information to a 256 word PSS memory in a random fashion. The PSS memory is addressed by an 8-bit port ID (SPIA_RX[32, 64 or 128]_PORT_ID[7:0]). The data written to the memory is the SPIA_RX[32, 64 or 128]_STAT and an external status enable (SPIA_RX[32, 64 or 128]_EXT_STAT_EN) for the selected port. A write is initiated by the FPGA by asserting SPIA_RX[32, 64 or 128]_PSS_WE high and providing a clock on SPIA_RX[32, 64 or 128]_PSS_CLK. The PSS block contains a main and shadow calendar table. Only one of these calendars is in use at a given time. Once a calendar is provisioned with a certain sequence, it is not desirable to change the sequence in that calendar during active device operation. To enable hitless switching of calendars, a shadow calendar is provided. The RX_CAL_SEL control bit (Address 30916 for SPIA and 30A16 for SPIB) in the memory map controls the choice. The choice to select a shadow calendar enables hitless bandwidth reprovisioning on the SPI4 link. While one calendar is being used (e.g. main), the other calendar (shadow) can be configured independently with the desired sequence. For more details, refer to the section on calendar programming. The Port Status Sequencer (PSS) block polls for port status. It uses the calendar address to decide which port should be polled for status. The status received from the polled port is then formatted into one of the SPI4 specified status encodings (STARVING, HUNGRY, SATISFIED). For every port, the status is polled either from the internal DPRAM FIFO flags or the user-provided status bits depending on the external status enable bit. When the external status enable bit for a given port is set to `1', it indicates that the status encoding for that port on the SPI4 bus is decided by the external user. When set to `0', the SPI4 status encoding is dictated by the status flags from the internal DPRAM banks. The status bits sent to RSP from the PSS block is determined according to the truth table shown in Table 22. The first four columns are the bits of information looked up for the current port ID, and the last column is the status that is sent for that selected port to the RSP.
Table 22. Port Status Encoding
Virtual FIFO fill 3 4 1 0 0 0 0 0 0
k = RX32 or RX64 or RX128
Virtual FIFO fill 1 2 x x x x 0 1 x
SPI[A,B]_k_EX SPI[A,B]_k_ST T_STAT_EN AT[1:0] x 1 1 1 0 0 1 x "00" "01" "10" x x "11"
SPI4 Status Encoding SATISFIED STARVING HUNGRY SATISFIED STARVING HUNGRY Disabled link
SPI4 Status Logic Blocks (RSP, RSO) The SPI4 Receive Status Protocol (RSP) is responsible for FIFO status encoding, calendar management, status pattern encoding (sync bits "11"), DIP-2 calculation and optional calendar selection word encoding (as proposed in Appendix G of SPI4-02.0 specification). The RSP block performs the following functions: * Status frame creation
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* Decrements CALENDAR_M and CALENDAR_LEN counters * DIP-2 calculation
ORCA ORSPI4 Data Sheet
The core of the RSP block is the state machine shown in Figure 32. The state machine is in the DISABLE state upon reset. Setting the register bit RX_STATUS_DIS to `1' or misalignment on the SPI4 RX data interface will cause the state machine to reset to DISABLE state and start sending "11" on the SPI4 status bus. When the received data is aligned and none of the other conditions apply, the state machine transfers to the SYNC state. The SYNC state exists for only one clock cycle. In this state the calendar management counters are initialized with the configured values from CALENDAR_LEN_RX and CALENDAR_M_RX. The next state is the CAL state if CALENDAR_SW_EN bit is set to `0' or the SWITCH state if CALENDAR_SW_EN bit is set to `1'. In the CAL state, the counter for CALENDAR_LEN_RX is decremented on each cycle and the counter for CALENDAR_M_RX is decremented at the end of each calendar sequence. If the CALENDAR_M_RX counter has not reached zero, the CALENDAR_LEN_RX counter is reset. On each clock cycle, the status is sent out on the RLSTAT bus. The DIP-2 code is calculated in each clock cycle using the method (diagonal XOR) described in the OIF-SPI4-02.0 standard. Once both calendar management counters have expired, the calendar management is complete and moves to the DIP-2 state. The current DIP-2 value coming out of the CAL state is XOR'ed with "11", the final 2-bit DIP-2 word is sent out on the RLSTAT bus and the SYNC state is entered. If the RX_CAL_SW_EN bit is enabled (set to `1') then the RSP will insert an extra word into the FIFO status frame
Figure 32. RSP State Machine
RESET DESKEWED RX_CALENDAR_SW_EN = `1' DISABLE RESET RESET RESET RX_CALENDAR_SW_EN= "0" SWITCH SYNC
DIP-2 CAL_DONE
CAL RX_CAL_LEN_MAIN/SHD, RX_CAL_M_MAIN/SHD
The SPI4 Receive Status Output (RSO) block contains the low speed LVTTL buffers and LVDS output buffers necessary for the output stage of receive status logic. The option to choose between LVTTL or LVDS outputs is selected by the software register bit SPI4_STATUS_IO_SEL. Calendar Programming On a SPI4 link, FIFO status information is sent periodically over the status link (RSTAT bus on the SPI4 interface) from the device that receives data. The calendar is a means by which the SPI4 link conveys information to a data source about the availability of buffer space in the FIFOs that receive data from that data source. A calendar is a sequence of status messages that * Provides information on the buffer space for a port or traffic flow * Allows user to allocate bandwidth for a port or flow depending on the overall traffic characteristics.
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ORCA ORSPI4 Data Sheet
The SPI4 status channel operates at 1/8th the SPI4 data rate which is reasonable because data is always sent in 16-byte bursts. Thus the fastest status update can be expected once in every 8 data clock cycles. For a given port, the frequency with which its status is reported to the far-end transmitter source depends on the allocated bandwidth for the port. It is imperative that the transmitter and receiver devices are programmed with identical calendar sequences. The following examples illustrate this: Suppose a channelized STS-48 has three STS-12 ports and four STS-3 ports (channels), each STS-12 port should have four times the bandwidth of an STS-3 port and 12 times the bandwidth of an STS-1 port within a single calendar cycle. The first step is to map each port to an 8-bit port ID (address) as shown in Table 23
Table 23. Port ID Mapping
Port A1 A2 A3 B1 B2 B3 B4 Bandwidth STS-12 STS-12 STS-12 STS-3 STS-3 STS-3 STS-3 8-Bit Port ID (Port Address) 0x00 0x01 0x02 0x03 0x04 0x05 0x06
The calendar sequence is as follows: A1, A2, A3, B1, A1, A2, A3, B2, A1, A2, A3, B3, A1, A2, A3, B4 The number of calendar entries is thus 16. This calendar sequence is programmed in the receive calendar memory as follows: * This example uses the main calendar. The calendar memory is selected by setting the RX_CAL_MEM_SEL bit (address 30917 in SPIA and address 30A17 in SPIB) to `1'. * Writes are done to addresses 0x31000 - 0x3100F. This will correspond to entries 0x00 - 0x0F in the calendar memory. This is shown in Table 24. Note that the main calendar memory has 1023 locations and can be programmed through addresses 0x31000 - 0x313FE. The shadow calendar memory also has 1023 locations and can be programmed through addresses 0x31400 - 0x317FE. * After programming the calendar memory, the RX_CAL_MEM_SET bit is set to `0'. * The calendar length register RX_CAL_LEN_MAIN is set to 16 (address 30901 and 30902 in SPIA, 30A01 and 30A02 in SPIB). * RX_CAL_M_MAIN (address 30900 in SPIA and 30A00 in SPIB) is set to the number of times the calendar sequence needs to be repeated between framing patterns. * The shadow calendar can be programmed in the same identical fashion as the main calendar using the steps described above. To enable hitless switching between main and shadow calendar memories, the RX_CAL_SW_EN bit (address 30916 in SPIA and 30A16 in SPIB) should be set to `1'. This will cause the receive status logic to insert the calendar select word after the framing pattern. The RX_CAL_SEL bit then selects main (bit set to `0') or shadow (bit set to `1') calendar to be sent on the outgoing status frame. It is important to enable this feature in the transmit device on the other end of the SPI4 link by setting TX_CAL_SW_EN bit (address 30916 in SPIA and 30A16 in SPIB) to `1'. This will cause the far-end transmit status logic to detect the calendar select word after the framing pattern.
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Table 24. Receive Calendar Memory Contents
RX Calendar Memory Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f RX Calendar Memory Contents (Port ID) 0x00 0x01 0x02 0x03 0x00 0x01 0x02 0x04 0x00 0x01 0x02 0x05 0x00 0x01 0x02 0x06
ORCA ORSPI4 Data Sheet
Port Number A1 A2 A3 B1 A1 A2 A3 B2 A1 A2 A3 B3 A1 A2 A3 B4
SPI4 Receive Software Interface
The SPI4 receive interface is configurable through a System Bus interface incorporated within the embedded core. The user can gain access to the System Bus either through the integrated MPI interface, or through FPGA resources using the System Bus Master/Slave interface. Please refer to the appropriate Lattice Semiconductor data sheets and application notes for more information regarding these interfaces. The receive SPI4 interface logic incorporates many configurable control registers, as well as interrupt and status registers to monitor SPI4 performance. Table 47 provides a memory map and description of each register within the Transmit portion of the SPI4 embedded core.
Timing Diagrams
As described earlier, there are three main modes of operation - 32-bit mode, 64-bit mode and 128-bit mode. The timing diagrams described below provide a clear picture of each mode of operation. For clarity, all timing diagrams are shown for SPIA core. They are identical for the SPIB core. The timing diagram for a 32-bit read access is shown in Figure 33. A 3-bit read address SPIA_RX32_ADDR_j where j=0,1,2,3 (which is actually the virtual FIFO partition address) is sent from the FPGA during clock T1. This FIFO address should match the virtual FIFO address that the user configured for a given port in the port descriptor memory (PDM). In other words, the virtual FIFO addressed by this 3-bit address contains the data for the port that was mapped to this buffer space in the PDM. The read control logic uses this address to generate the internal physical address. As shown in Figure 33, the user sends SPIA_RX32_RD_j in clock cycle T1. There is a 2-clock latency from the time the read enable SPIA_RX32_RD_j is asserted to the time read data is presented to the user. Thus, in clock cycle T3 following SPIA_RX32_RD_j, the embedded core provides the 32-bit data and control. The byte enables SPIA_RX32_BE_j[3:0] indicate which bytes within the 32-bit word are valid. If the current port ID is different from the previous port ID, then the first data read from the virtual FIFO is the port ID as shown in clock cycle T3. The SPIA_RX32_CTL_j signal is set to `1' during T3 indicating that read data contains the port ID. The byte enables are set to "0001" indicating that the least significant byte of the 32-bit word contains the port ID. If data is continued to be read for the same port, then no port ID is presented to the user as this is redundant. The ASTOP_ON_EOPj is 86
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
set to `0' which means that the core will terminate a 4-word burst when EOP occurs and start transmission of the next set of data. Note that a new FIFO address `p' is provided during the last 4-word burst of address `n'. This absorbs the 2-clock latency from the time a new address is presented to the DPRAM and the time read data is presented to the user. As shown in Figure 34, when the ASTOP_ON_EOPj is asserted, 2 idle clock cycles are inserted after an EOP occurs. During these idle cycles, the byte enable bits are set to all `0's indicating that the read data is not valid. After the idle cycles, the core continues to provide read data. The ASTOP_ON_EOPj signal can be asserted anytime and held high for any length of time during a read data transfer. At any time, the user can poll for the status of a FIFO within a DPRAM bank by providing just the read address SPIA_RX32_ADDR_j without providing the read enable. Note that the timing diagram shown in Figure 33 and Figure 34 indicate a FIFO size of 16 locations. Each location contains four 32-bit data words. Thus when SPIA_RX32_FIFO_EMPTY_j flag is `1' and RX_DPRAM_EMPTY_TYPE_SELA[j] software register bit in address 30920 is set to `1', it implies that the FIFO has three 4-word data left (1/4 * 16 locations - 1). As shown in Figure 35, the ERR signal indicates that the corresponding packet is in error. The ERR signal can be asserted by the ORSPI4 core several clock cycles before EOP and remains asserted until EOP occurs. However, the user is always required to use the ERR signal in conjunction with the EOP signal. Irrespective of the ERR signal being asserted, the core always transmits the entire packet. Thus, it is relevant for the user application to sample the ERR signal simultaneously with EOP. Users should also be aware that this is in asymmetry with the transmit SPI4 core's behavior. In the transmit direction, user always asserts ERR signal during an EOP only. Thus, if any loopback is performed from the receive SPI4 (A or B) to the transmit SPI4 (A or B), the user should ensure that the received ERR signal is not wired directly to the corresponding transmit ERR signal, but follows the transmit protocol of providing an ERR signal only in the same clock cycle as an EOP and not earlier.
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Figure 33. Read Timing with ASTOP_ON_EOP Deasserted - 32-Bit Mode
J=0-3
ORCA ORSPI4 Data Sheet
FIFO size = 16 locations. 1 SPIA_RX32_ CLK_j 2 3 4 5 6 .... ....
SPIA_RX32_RD_j SPIA_RX32_ADDR_j n
FIFO address changes during last 4-word burst of address n p Empty flag is low for FIFO address p
SPIA_RX32_FIFO_ EMPTY_j
Addressed by n, FIFO has three 4-word 2 cycles after read enable bursts of data ....
SPIA_RX32_DATA_j[31:0]
Port ID SPIA_RX32_BE_jj[3:0] 0001
na
nb
nc
nd
nb
nc
nd
pa First word of address p
1111
1111
1111
1111
....
1111
1111
SPIA_RX32_ERR_j
SPIA_RX32_CTL_j
SPIA_RX32_SOP_j
SPIA_RX32_EOP_j
ASTOP_ON_EOPj
na = word 0 from pointer location in FIFO address n nb = word 1 nc = word 2 nd = word 3
pa = word 0 from pointer location in address p
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Figure 34. Read Timing with ASTOP_ON_EOP Asserted - 32-Bit Mode
J=0-3 SPIA_RX32_ CLK_j 1 2 3 4 5 6 ....
ORCA ORSPI4 Data Sheet
FIFO size = 16 locations. ....
SPIA_RX32_RD_j SPIA_RX32_ADDR_j n SPIA_RX32_FIFO_ EMPTY_j 2 cycles after read enable Idle cycles inserted
SPIA_RX32_DATA_j[31:0]
Port ID
na
nb
nc
nd
na
nb
SPIA_RX32_CTL_j
SPIA_RX32_SOP_j
SPIA_RX32_EOP_j
SPIA_RX32_ERR_j
ASTOP_ON_EOPj
SPIA_RX32_BE_j[3:0] h1 hf hf hf hf h0 h0 hf hf
na = word 0 from pointer location in FIFO address n nb = word 1 nc = word 2 nd = word 3
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Figure 35. Read Timing with ERR Signal Asserted - 32-Bit Mode
J=0-3 SPIA_RX32_ CLK_j 1 2 3 4 5 6 ....
ORCA ORSPI4 Data Sheet
FIFO size = 16 locations. ....
SPIA_RX32_RD_j SPIA_RX32_ADDR_j n
SPIA_RX32_FIFO_ EMPTY_j 2 cycles after read enable SPIA_RX32_DATA_j[31:0] Port ID na nb nc nd na nb nc nd
SPIA_RX32_CTL_j
SPIA_RX32_SOP_j
SPIA_RX32_EOP_j
SPIA_RX32_ERR_j
ASTOP_ON_EOPj SPIA_RX32_BE_j[3:0] h1 hf hf hf hf h8 hf hf hf
na = word 0 from pointer location in FIFO address n nb = word 1 nc = word 2 nd = word 3
In the 64-bit data aggregation mode, DPRAMs 0 and 1 are used as a single memory. Similarly, DPRAMs 2 and 3 are combined into a single memory. The timing diagrams for the 64-bit aggregation mode are shown in Figure 36, Figure 37 and Figure 38. As shown in the timing diagrams, read data is always presented to the user in 2 clock cycles of 64-bit data each (plus one additional clock cycle for port ID). The exception is during an EOP. If EOP occurs during the first of the two-word data burst, the core terminates the burst and starts to present the next set of data. As shown in Figure 36, there is a two-clock cycle latency between the time read enable is asserted by the user and the time data is read from a virtual FIFO. In clock cycle T1, the read enable signal SPIA_RX64_RD_j is asserted along with the virtual FIFO (or buffer) address SPIA_RX64_ADDR_j. In clock cycle T3, port ID is presented followed by two data words in clock cycles T4 and T5. The port ID is always present on the least significant byte. This is indicated by the byte enable bits set to "00000001". As shown in Figure 36, FIFO address is changed to `p' during the last two-word burst from address `n'. This is done to absorb the two-clock cycle latency between read address and data. As shown in Figure 37, when the ASTOP_ON_EOPj is asserted, two idle clock cycles are inserted after an EOP occurs. During these idle cycles, the byte enable bits are set to all `0's indicating that the read data is not valid. After
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ORCA ORSPI4 Data Sheet
the idle cycles, the core continues to provide read data. The ASTOP_ON_EOPj signal can be asserted anytime and held high for any length of time during a read data transfer. At any time, the user can poll for the status of a FIFO within a DPRAM bank by providing just the read address SPIA_RX64_ADDR_j without providing the read enable. Note that the timing diagram shown in Figure 36, Figure 37 and Figure 38 indicate a FIFO size of 32 locations. Each location contains two 64-bit data words. Thus when SPIA_RX64_FIFO_EMPTY_j flag is `1' and RX_DPRAM_EMPTY_TYPE_SELA[j] software register bit in address 30920 is set to `1', it implies that the FIFO has 7 two-word data left (1/4 * 32 locations - 1). As shown in Figure 38, the ERR signal indicates that the corresponding packet is in error. The ERR signal can be asserted by the ORSPI4 core several clock cycles before EOP and remains asserted until the clock cycle when EOP is asserted. However, the user is always required to use the ERR signal in conjunction with the EOP signal. Irrespective of the ERR signal being asserted, the core always transmits the entire packet. Thus, it is relevant for the user application to sample the ERR signal simultaneously with EOP. Users should also be aware that this is in asymmetry with the transmit SPI4 core's behavior. In the transmit direction, user always asserts ERR signal during an EOP only. Thus, if any loopback is performed from the receive SPI4 (A or B) to the transmit SPI4 (A or B), the user should ensure that the received ERR signal is not wired directly to the corresponding transmit ERR signal, but follows the transmit protocol of providing an ERR signal only in the same clock cycle as an EOP and not earlier.
Figure 36. Read Timing with ASTOP_ON_EOP Deasserted - 64-Bit Mode
j=0,1 SPIA_RX64_CLK_j 1 2 3 4 5 6 .... .... FIFO size = 32
SPIA_RX64_RD_j Address changed to partition/FIFO p during last 2-word burst in address n
SPIA_RX64_ADDR_j
n
p FIFO empty low for address p Indicates FIFO has seven 2-word bursts
SPIA_RX64_FIFO_EMPTY_j
SPIA_RX64_DATA_j[63:0] Port ID SPIA_RX64_BE_j[7:0] h01 hff hff .... hff hff h01 na nb .... na nb Port ID pa
SPIA_RX64_CTL_j
SPIA_RX64_SOP_j
SPIA_RX64_EOP_j
SPIA_RX64_ERR_j
ASTOP_ON_EOPj
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Figure 37. Read Timing with ASTOP_ON_EOP Asserted - 64-Bit Mode
SPIA_RX64_CLK_j 1 2 j = 0,1 3 4 5 6 ....
ORCA ORSPI4 Data Sheet
FIFO size = 32 locations. ....
SPIA_RX64_RD_j SPIA_RX64_ADDR_j n
SPIA_RX64_FIFO_EMPTY_j 2 cycles after read SPIA_RX64_DATA_j[63:0] Port ID enable na nb na nb na nb Idle cycles inserted
SPIA_RX64_CTL_j
SPIA_RX64_SOP_j
SPIA_RX64_EOP_j
SPIA_RX64_ERR_j
ASTOP_ON_EOPj
SPIA_RX64_BE_j[7:0] h01 hff hff hff hff h00 h00 hff hff
na = word 0 from pointer location in FIFO address n nb = word 1
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Lattice Semiconductor
Figure 38. Read Timing with ERR Asserted - 64-Bit Mode
SPIA_RX64_CLK_j j = 0,1 1 2 3 4 5 6 ....
ORCA ORSPI4 Data Sheet
FIFO size = 32 locations. ....
SPIA_RX64_RD_j SPIA_RX64_ADDR_j n
SPIA_RX64_FIFO_EMPTY_j 2 cycles after read SPIA_RX64_DATA_j[63:0] Port ID enable na nb na nb na nb na nb
SPIA_RX64_CTL_j
SPIA_RX64_SOP_j
SPIA_RX64_EOP_j
SPIA_RX64_ERR_j
ASTOP_ON_EOPj
SPIA_RX64_BE_j[7:0] h01 hff hff hff hff hff hff hff hff
na = word 0 from pointer location in nb = word 1
FIFO address n
In the 128-bit data aggregation mode, DPRAMs 0,1,2 and 3 are used as a single contiguous memory. All DPRAMs must be configured identically by software. In 128-bit aggregation mode, a maximum of 8 per-port buffers are possible. One significant difference between the 128-bit mode and the 32-bit and 64-bit modes is that the port ID is presented to the user on a separate bus (SPIA_RX128_PORTID[7:0]). Thus the SPIA_RX128_CTL signal has no relevance to the user and can be ignored. Read data is presented as a 128-bit word every clock cycle. As shown in Figure 39, read enable SPIA_RX128_RD and address SPIA_RX128_ADDR are presented in clock cycle T1. In T3 read data is available to the user after 2 clock cycles of latency. The FIFO address is changed to `p' during the second last word of address `n' such that the 2 clock cycles of latency between address and data can be absorbed. As shown in Figure 40, when the ASTOP_ON_EOP is asserted, two idle clock cycles are inserted after an EOP occurs. During these idle cycles, the byte enable bits are set to all `0s indicating that the read data is not valid. After the idle cycles, the core continues to provide read data. The ASTOP_ON_EOP signal can be asserted anytime and held high for any length of time during a read data transfer. At any time, the user can poll for the status of a FIFO within a DPRAM bank by providing just the read address SPIA_RX128_ADDR without providing the read enable. Note that the timing diagram shown in Figure 39, Figure 40 and Figure 41 indicate a FIFO size of 64 locations. Each location contains a 128-bit word. Thus when
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ORCA ORSPI4 Data Sheet
SPIA_RX128_FIFO_EMPTY flag is `1' and RX_DPRAM_EMPTY_TYPE_SELA[0:3] software register bits in address 30920 are set to `1', it implies that the FIFO has 15 128-bit words left (1/4 * 64 locations - 1). As shown in Figure 41, the ERR signal indicates that the corresponding packet is in error. The ERR signal can be asserted by the ORSPI4 core several clock cycles before EOP and remains asserted until the clock cycle when EOP is asserted. However, the user is always required to use the ERR signal in conjunction with the EOP signal. Irrespective of the ERR signal being asserted, the core always transmits the entire packet. Thus, it is relevant for the user application to sample the ERR signal simultaneously with EOP. Users should also be aware that this is in asymmetry with the transmit SPI4 core's behavior. In the transmit direction, user always asserts ERR signal during an EOP only. Thus, if any loopback is performed from the receive SPI4 (A or B) to the transmit SPI4 (A or B), the user should ensure that the received ERR signal is not wired directly to the corresponding transmit ERR signal, but follows the transmit protocol of providing an ERR signal only in the same clock cycle as an EOP and not earlier.
Figure 39. Read Timing with ASTOP_ON_EOP Deasserted - 128-Bit Aggregation Mode
FIFO size = 64 SPIA_RX128_CLK 1 2 3 4 5 6
....
SPIA_RX128_RD Address changed when penultimate word is read from FIFO n p FIFO empty for address p Data read 2 cycles after Address changed to p
SPIA_RX128_ADDR
n
SPIA_RX128_EMPTY 2 cycles after SPIA_RX128_DATA read enable D0 D1 D2 ....
Indicates FIFO has 15 words left
D62
D63
P0
SPIA_RX128_PORTID Port ID
Port ID SPIA_RX128_BE hffff hffff .... hffff hffff
SPIA_RX128_SOP
SPIA_RX128_EOP
SPIA_RX128_ERR
ASTOP_ON_EOP
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Lattice Semiconductor
Figure 40. Read Timing with ASTOP_ON_EOP Asserted - 128-Bit Mode
ORCA ORSPI4 Data Sheet
FIFO size = 64 locations. SPIA_RX128_CLK 1 2 3 4 5 6 .... ....
SPIA_RX128_RD SPIA_RX128_ADDR n
SPIA_RX128_FIFO_EMPTY 2 cycles after read SPIA_RX128_DATA D0 enable D1 D2 D3 D4 Idle cycles inserted
D0
D1
SPIA_RX128_SOP
SPIA_RX128_EOP
SPIA_RX128_ERR
ASTOP_ON_EOP SPIA_RX128_BE hffff hffff hffff hffff hffff h0000 h0000 hffff hffff
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Lattice Semiconductor
Figure 41. Read Timing with ERR Asserted - 128-Bit Mode
ORCA ORSPI4 Data Sheet
FIFO size = 64 locations. SPIA_RX128_CLK 1 2 3 4 5 6 .... ....
SPIA_RX128_RD SPIA_RX128_ADDR n
SPIA_RX128_FIFO_EMPTY
2 cycles after read SPIA_RX128_DATA D0 enable D1 D2 D3 D4 D0 D1 D2 D3
SPIA_RX128_SOP
SPIA_RX128_EOP
SPIA_RX128_ERR
ASTOP_ON_EOP
SPIA_RX128_BE hffff hffff hffff hffff hffff hffff hffff hffff hffff
Special Operating Modes
Static Capture Mode The ORSPI4 receiver supports both dynamic and static capture of data at the high-speed SPI4 interface. All the operating modes (32-bit, 64-bit and 128-bit) are independent of the type of data capture. They can operate in either static or dynamic capture mode. The choice of static vs. dynamic alignment depends on the SPI4 data rates. The static data capture is valid in the frequency range 400-700 Mbps. It also reduces the power dissipation of the device. The following control signals are relevant to enable static data capture: SPI4_LOW_SPEED_DATA_SEL: This is a software register control bit (Address 30915 in SPIA and 30A15 in SPIB). When set to `0', the dynamic alignment circuit is held in a reset state and the static alignment mode is enabled. SPI_DATM_A or SPI_DATM_B: This is a control signal from the FPGA. When set to `1', this gives the user the option to skew the RDCLK with respect to the SPI4 data bus RDAT on the bus by choosing delay taps through the control bits SPI_DLYTAP_A[2:0] of SPI_DLYTAP_B[2:0]. When set to `0', RDCLK is automatically centered on-chip to the input data bus RDAT. Quarter-Rate Mode
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ORCA ORSPI4 Data Sheet
The ORSPI4 SPI4 RX interface is also designed to operate at data rates much lower than 622 Mbps. Even though the OIF standard specifies a minimum data rate of 622 Mbits/s, the lower data rates are provided for users who wish to use the SPI4 link for applications supporting <10 Gbits/s aggregate bandwidth (STS-48, STS-3, Gb Ethernet, etc.). To enable this low speed mode, user should set the software register bit SPI4_QUARTER_RATE (Address 30915 in SPIA and 30A15 in SPIB) to `1'. This supports data rates in the range of 100 - 200 Mbps. This bit takes precedence over SPI4_LOW_SPEED_DATA_SEL, since setting this bit to `1' will automatically reset the dynamic alignment block irrespective of SPI4_LOW_SPEED_DATA_SEL register bit setting.
SPI4 Loopback Modes
There are three forms of loopback supported directly by the ORSPI4 SPI4 blocks. * High-speed near end loopback: This involves looping back data from the high-speed transmit block TDO serial output to the high-speed receive block RDI serial input (See Fig. 42). All of the logic excluding the LVDS buffers is included in the loopback path. The status path is looped from the output of the RSP block to the TSP block. This mode is enabled by setting the control register bit SPI4_LOOPBK_HS to 1. * Far end loopback: This involves looping back the 128-bit output data from the RDI block to the 128-bit input of the TDO block (See Fig. 43). Data is received at the high-speed SPI4 RX interface and transmitted at the SPI4 TX interface. The status path is looped from TSTAT to RSTAT. This mode is enabled by setting control register bit SPI4_LOOPBK_FE to "1". * Low-speed near end loopback which excludes the high-speed blocks from the loopback path: This involves sourcing data from the FPGA, looping back the output of TDP block into RDP block and observing data at the core-FPGA boundary (See Fig. 44). The status path is looped from the RSP block to the TSP block. This form of loopback will require an additional low-speed clock source (TSTCLK) and is enabled by setting control register bit SPI4_LOOPBK_LS to "1" and enabling SPI4_LOOPBK_HS.
Figure 42. High-Speed Near End Loopback
Embedded Core DPRAMs + associated logic FPGA TX SPI4 I/F
TDAT[15:0]
TDP
128-bit data+ctl
TDO
TCTL TDCLK TREFCLK
Port write Sequencer
TSTAT[1:0]
TSP
clk
TSCLK
RX DPRAMs + associated logic
128-bit data+ctl
RDAT[15:0]
RDP
clk
RDI
RCTL RDCLK
RSTAT[1:0]
Port Status Sequencer
RSP
clk
RSCLK
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ORCA ORSPI4 Data Sheet
Figure 43. Far End Loopback
TX FPGA Embedded Core DPRAMs + associated logic TDP
128-bit data+ctl
SPI4 I/F
TDAT[15:0]
TDO
TCTL TDCLK TREFCLK TSTAT[1:0]
Port write Sequencer
TSP
TSI
TSCLK
RX DPRAMs + associated logic
128-bit data+ctl
RDAT[15:0]
RDP
clk
RDI
RCTL RDCLK
RSTAT[1:0]
Port Status Sequencer
RSP
clk
RSO
RSCLK
Far End Loopback Setup The following three step procedure will set up the ORSPI4 into far end loopback mode: 1. Set up the external connections to the ORSPI4 such that the RDAT, RDCLK, and RCTL SPI-4 ports are all receiving signals. (If in quarter rate mode, the FPGA-sourced clock reference signal SPI[A,B]_TREFCLK_X8 must be supplied at twice the rate as the applied [A,B]RDCLK SPI-4 port clock. 2. Configure the appropriate ORSPI4 register as shown in Table 25. Note that either choice of LVTTL or LVDS for status buffer is acceptable for far end loopback, although the choice will affect the status port timing. Also note that bits 6 and 7 (TX_FORCE_DIP4_ERR and RX_FORCE_DIP2_ERR) do not affect the operation of far end loopback. 3. Reset the appropriate SPI4 block with control signal FPGA_RESET_S4[A,B].
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Table 25. Far End Loopback Register Values
Absolute Address (Hex)
ORCA ORSPI4 Data Sheet
Bit [0]
Name
Description
Quarter Rate Far End 1
Static Dynamic Far End Far End 0 0
When set to `1', enables data rates of 100 - 200 SPI4_QUARTER_RATE Mbps. The PLLs in the transmit and receive SPI4 high-speed blocks are bypassed in this mode. This control enables far-end loopback when it is set to 1. Far end loopback sends RDAT inputs back to TDAT outputs, sends RDCLK back to TDCLK, sends TSTAT back to RSTAT outputs, and ATSCLK back to RSCLK. Forces low speed data rates of 400-622 Mbits/s. The transmit PLL is still used to synthesize the SPI4 transmit clock TDCLK. However, the dynamic alignment block in the receive side is bypassed. No training sequences are used in low speed mode. `0' - Selects LVTTL I/O for SPI4 status. `1' - Selects LVDS I/Os for SPI4 status (Full-rate LVDS status I/Os specified by OIF SPI4.0 is not supported). Enables loops from high-speed SPI4 TDAT outputs to RDAT inputs and RSTAT to TSTAT status inputs just before I/O. Enables near-end parallel loopback from TDP to RDP blocks and RSP to TSP blocks bypassing the high-speed SPI4 interface logic blocks. Must enable SPI4_LOOPBK_HS for this to work.
[1]
SPI4_LOOPBK_FE
1
1
1
[2] 30915 (SPI A) 30A15 (SPI B)
SPI4_LOW_SPEED_ DATA_SEL
1
1
0
[3]
SPI4_STATUS_IO_SEL
0 or 1
0 or 1
0 or 1
[4]
SPI4_LOOPBK_HS
0
0
0
[5]
SPI4_LOOPBK_LS
0 X X
0 X X
0 X X
[6] TX_FORCE_DIP4_ERR [7] RX_FORCE_DIP2_ERR
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Lattice Semiconductor
Figure 44. Low-Speed Near End Loopback (Excluding High-Speed Blocks)
TX Embedded Core DPRAMs + associated logic FPGA TDP b
ORCA ORSPI4 Data Sheet
SPI4 I/F 128-bit data+ctl TDO
TDAT[15:0] TCTL TDCLK TREFCLK TSTAT[1:0]
Port write Sequencer
TSP
clk
TSCLK
RX DPRAMs + associated logic
128-bit data+ctl RDP clk RDI
RDAT[15:0] RCTL RDCLK
Port Status Sequencer
RSTAT[1:0]
RSP
clk
RSCLK
SPI4 Error Insertion Capabilities
The SPI4 blocks support the following error insertion options for testing: * DIP-4 odd parity is calculated over data and control words on the TX side. Under software control, DIP-4 errors can be forced by inverting the DIP-4 parity bits. This is done by setting TX_FORCE_DIP4_ERR bit to `1' (Address 30915 in SPIA and 30A15 in SPIB). * DIP-2 odd parity is calculated over the status frames on the RX side. Under software control, DIP-2 errors can be forced by inverting the DIP-2 parity bits. This feature can be enabled by setting RX_FORCE_DIP2_ERR to `1' (Address 30915 in SPIA and 30A15 in SPIB).
SPI4 Status Reporting Capabilities
The following status information will be reported through status registers. Most status registers also cause interrupts. The interrupts can be masked by the corresponding interrupt enables. * DIP-4, DIP-2 errors (These cause interrupts). The associated register status bits are: - RX_ALGN_OFF_STS, TX_STATUS_LOF_STS, RX_DIP4_ERR_STS, TX_DIP2_ERR_STS * DIP-4, DIP-2 error counters. These are 8-bit counters. The status registers are: - RX_DIP4_ERR_CNT, TX_DIP2_ERR_CNT * Deskew status and error from high-speed RX side. These cause an interrupt. The associated register status bits are: - RX_DSKW_DONE_STS, RX_DSKW_ERR_STS - DPRAM FIFO overruns and underruns (RX and TX DPRAM memories). These can cause an interrupt. - SPIA or SPIB Receive PLL Loss of lock indicator. The associated register bit is -RX_PLL_LOL_STS
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Lattice Semiconductor ORSPI4 SPI4 Clocking
ORCA ORSPI4 Data Sheet
Transmit Clocking The following descriptions and figures show the SPIA core. The SPIB core is identical.
Figure 45. SPI4 TX Clocking
k= 32, 64, or 128
FPGA
SPIA_TXk_CLK_0 SPIA_TXk_CLK_1 SPIA_TXk_CLK_2 SPIA_TXk_CLK_3 SPIA_TREFCLK_x8 ATREFCLK_F ATREFCLK
SPIA TX Core (Data)
ATDCLKP ATDCLKN
ATSCLKP
SPIA TX Status
ATSCLKN TSCLKA
LVDS Input LVTTL Input
ATREFCLK: External Pad. Reference clock for the high-speed SPIA transmit block. Its frequency is 1/4th the SPI4 line clock ATDCLK. The ATREFCLK pad should be tied off during quarter-rate mode. SPIA_TREFCLK_x8: Reference clock source from the FPGA when SPIA is operating in quarter-rate mode. Its frequency is two times the SPI4 line clock. i.e. if SPI4 line clock is 100 MHz, this clock is 200 MHz. Maximum allowable frequency is 200 MHz. ATDCLK[P,N]: External output pads. SPI4 transmit data clock. SPI4 transmit data ATDAT and ATCTL are valid on both edges of this clock. ATSCLK[P,N]: External input LVDS pads. SPI4 transmit status clock. TSCLKA: External input 3.3V LVTTL transmit status input. SPIA_TXk_CLK_j: Write clocks from FPGA to each of the four asynchronous DPRAMs. (j = 0, 1, 2 or 3) (k = 32, 64 or 128) ATREFCLK_F: Clock output to the FPGA. Its frequency is the same as ATREFCLK. It is used to clock the status outputs to the FPGA, namely SPIA_TXk_PORT_ID, SPIA_TXk_STAT and SPIA_TXk_BURST_VAL.
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ORCA ORSPI4 Data Sheet
Receive Clocking The following descriptions and figures show the SPIA core. The SPIB core is identical.
Figure 46. SPI4 RX Clocking
k = 32, 64, or 128 j =0, 1, 2 or 3
FPGA
SPIA_RXk_CLK_0 SPIA_RXk_CLK_1 SPIA_RXk_CLK_2 SPIA_RXk_CLK_3 ARDCLKP
SPIA RX Core (Data)
ARDCLKN
SPIA_RXk_PSS_CLK ARLSCLK_F
ARSCLKP
SPIA RX Status
ARSCLKN RSCLKA
LVDS Output LVTTL Input
ARDCLK[P,N]: SPI4 line clocks received with data and control. These are external LVDS input pads. SPIA_RXk_CLK_j: Read clocks to each of the four asynchronous DPRAMs. ARLSCLK_F: Output clock from receive status logic to FPGA. SPIA_RXk_PSS_CLK: Write clocks from FPGA to the receive status RAM. The ARLSCLK_F clock can be used to source this clock as shown by dotted lines in the figure. ARSCLK[P,N]: LVDS receive status outputs. External pads. RSCLKA: 3.3 V LVTTL receive status output. External pads.
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ORCA ORSPI4 Data Sheet
SERDES Functional Description
The SERDES portion of the ORSPI4 contains four Clock and Data Recovery (CDR) macrocells and Serialize/Deserialize (SERDES) blocks and supports 8b/10b (IEEE 802.3.2002) encoded serial links. It is intended for high-speed serial backplane data transmission. Figure 47 shows the SERDES top level block diagram and the basic data flow to and from the SERDES. Boundary scan for the SERDES only includes programmable I/Os and does not include any of the embedded block I/Os.
Figure 47. SERDES Top Level Block Diagram.
0.6 Gbits/s TO 3.7 Gbits/s DATA STANDARD FPGA I/Os
ORCA SERIES 4 FPGA LOGIC
BYTE- SERDES w/ 8b/10b WIDE CLOCK/DATA DECODER/ENCODER DATA RECOVERY 4:1 MUX/1:4 DEMUX
CML I/Os
4 FULLDUPLEX SERIAL CHANNELS
0.6 Gbits/s TO 3.7 Gbits/s DATA
The SERDES serial channels can each operate at up to 3.7 Gbits/s (2.96 Gbits/s data rate) with a full-duplex synchronous interface with built-in clock recovery (CDR). The 8b/10b encoding provides guaranteed ones density for the CDR, byte alignment, and error detection. The core is also capable of frame synchronization and physical link monitoring. Overviews of the various blocks in the SERDES are presented in the following paragraphs
ORSPI4 SERDES Functional Block Overview
The SERDES portion of the core contains one transceiver block for serial data transmission at a selectable data rate of 0.6-3.7 Gbits/s. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core blocks and high-speed CML interfaces to the serial links. The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts highspeed (up to 3.7 Gbits/s) serial data. Based on data transitions, the receiver locks an analog receive PLL for each channel to retime the data, then de-multiplexes the data down to parallel bytes and an accompanying clock. The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.7 Gbits/s serial data for offchip communication. The transmitter generates the necessary high-speed clocks for operation from a lower speed reference clock. The transceivers are controlled and configured through the system bus in the FPGA logic and through the external 8-bit microprocessor interface of the FPGA. Each channel has associated dedicated registers that are readable and write-able. There are also global registers for control of common circuitry and functions. The SERDES performs 8b/10b encoding and decoding for each channel. The 8b/10b transmission code can support either Ethernet or Fibre Channel specifications for serial encoding/decoding, special characters, and error detection. The user can disable the 8b/10b decoder to receive raw 10-bit words which will be rate reduced by the SERDES. If this mode is chosen, the user must bypass the multi-channel alignment FIFOs.
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ORCA ORSPI4 Data Sheet
The SERDES block contains its own dedicated PLLs for both transmit and receive clock generation. The user provides a reference clock of the appropriate frequency. The receiver PLLs extract the clock from the serial input data and retime the data with the recovered clock. MUX/DEMUX Block The MUX/DEMUX block converts the data format for the high-speed serial links to a wide, low-speed format for crossing the CORE/FPGA interface. The intermediate interface to the SERDES macrocell runs at 1/10th the bit rate of the data lane. The MUX/DEMUX converts the data rate and bus width so the interface to the FPGA core can run at 1/4th this intermediate frequency, giving a range of 25.0-92.5 MHz for the data rates into and out of the FPGA logic. Multi-Channel Alignment FIFOs The four incoming data channels can be independent of each other, or can be synchronized in several ways. Two channels within a SERDES block can be aligned together; channels A and B and/or channels C and D. Alternatively, four channels in a SERDES block can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. XAUI and Fibre Channel Link State Machines Two separate link state machines are included in the architecture. A XAUI link state machine is included in the SERDES, modeled after the IEEE 802.3ae standard. A separate state machine for Fibre Channel is also implemented. FPGA/SERDES Interface In 8b/10b mode, the FPGA logic will receive/transmit 32-bits of data (up to 92.5 MHz) and four K_CTRL bits from/to the SERDES. There are eight data streams in each direction plus additional timing, status and control signals. Data sent to the FPGA can be aligned using comma (/K/) characters or the /A/ character as specified either by Fibre Channel or by IEEE 802.3ae for XAUI based interfaces. The alignment character is made available to the FPGA along with the data. The special characters K28.1, K28.5 and K28.7 are treated as valid comma characters by the SERDES. If the receive channel alignment FIFOs are bypassed, then each channel will provide its own receive clock in addition to data and comma character detect signals. If the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in 8b/10b bypass mode. The following table summarizes the interface signals between the FPGA logic and the core. In the table, an input refers to a signal flowing into the SERDES and an output refers to a signal flowing out of the SERDES.
Table 26. FPGA/SERDES Interface Description
FPGA/Embedded Core Interface Signal Name (x = [A, ..,D]) Transmit Path Signals TWDx[31:0] TCOMMAx[3:0] TBIT9x[3:0] TSYS_CLK_x TCK78 Receive Path Signals MRWDx[39:0] RWCKx Core FPGA Core FPGA Receive data--Channel x (see Table 35). Low-speed receive clock--Channel x. FPGA Core Transmit data--channel x. FPGA Core Transmit comma character--channel x. FPGA Core Transmit force negative disparity--channel x FPGA Core Transmit low-speed clock to the FPGA--channel x Core FPGA Transmit low-speed clock to the FPGA--SERDES Quad Input (I) to or Output (O) from Core
Signal Description
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Lattice Semiconductor
RCK78 RSYS_CLK_1 RSYS_CLK_2 CV_SELx SYS_RST_N FPGA_RESET_FC Core FPGA
ORCA ORSPI4 Data Sheet
Receive low-speed clock to FPGA--SERDES Quad.
FPGA Core Low-speed receive FIFO clock for channels A, B FPGA Core Low-speed receive FIFO clock for channels C, D FPGA Core Enable detection of code violations in the incoming data FPGA Core Synchronous reset of the channel alignment blocks. FPGA Core Disables access to SERDES when high
Backplane Transceiver Core Detailed Description
The following sections describe the various logic blocks in the SERDES portion of the FPSC. For a detailed description of the programmable logic functions, please see the ORCA Series 4 FPGA Data Sheet and related application and technical notes. The major functional blocks in the SERDES include: * One SERializer-DESerializer (SERDES) block and Clock and Data Recovery (CDR) circuitry * 8b/10b encoder/decoders * Transmit pre-emphasis circuitry * 4-to-1 multiplexers (MUX) and 1-to-4 demultiplexers (DEMUX) * Fibre channel synchronization state machine * XAUI link alignment state machine * Alignment FIFOs A top level block diagram of the SERDES Logic is shown in Figure 48.
Figure 48. Top Level Block Diagram, SERDES Embedded Core Logic
RCK78 TCK78 Logic Common to Quad Receive Channel A MRWDA[39:0] CV_SELA RWCKA Multi Channel Alignment Block 2:1 MUX (x40) Link State Machine
2
REFCLK[P:N]
DEMUX Block
RX SERDES Block
2
HDIN[P:N]_A
TSYS_CLK_A TWDA[31:0] TCOMMA[3:0] Transmit Channel A Interface and MUX Block Channel B Channel C Channel D TX SERDES Block
2
Backplane Serial Links
HDOUT[P:N]_A
FPGA Logic
. . .
. . .
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Lattice Semiconductor SERDES Detailed Description
ORCA ORSPI4 Data Sheet
The SERDES provides transceiver functionality for four serial data channels. Each channel is identified by a channel identifier [A:D]. The data channels can operate independently or they can be combined together (aligned) to achieve higher bit rates. The mode operation of the core is defined by a set of control registers, which can be written through the system bus interface. Also, the status of the core is stored in a set of status registers, which can be read through the system bus interface. The transmitter section for each channel accepts 40 bits (RAW MODE) of data or 32-bits of data and eight control/status bits from the FPGA logic and (optionally) encodes the data using 8b/10b encoding. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to synthesize the internal high-speed serial bit clock. The data is then serialized and the serialized data are available at the differential CML output terminated in 86 to drive either an optical transmitter or coaxial media or circuit board/backplane. The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the clock recovery section, which generates a recovered clock and retimes the data. The retimed data are also de-serialized and optionally 8b/10b decoded. The receiver also (optionally) recognizes the comma characters or code violations and aligns the bit stream to the proper word boundary. The resulting parallel data is (optionally) passed to the multi-channel alignment block before it is presented to the FPGA logic. 8b/10b Encoding and Decoding In 8b/10b mode, the FPGA logic will receive/transmit 32-bits of data and four K_CTRL bits from/to the embedded core. In the transmit direction, four additional input bits can force a negative disparity present state. The SERDES logic will encode the data to, or decode the data from, a 10-bit format according to the FC-PH ANSI X3.230:1994 standard (which is also the encoding used by the IEEE 802.3ae Ethernet standard). This encoding/decoding scheme also allows for the transmission of special characters and supports error detection. Following the definitions and conventions used in defining the 8b/10b coding rules, each valid coded character has a name corresponding to its 8-bit binary value: * Dx.y for data characters * Kx.y for special characters * x = the 5-bit input value, base 10, for bits ABCDE * y = the 3-bit input value, base 10, for bits FGH An 8b/10b encoder is designed to maintain a neutral average disparity. Disparity is the difference between the number of "1"s and "0"s in the encoded word. Neutral disparity indicates the number of "1"s and "0"s are equal. Positive disparity indicates more "1"s than "0"s. Negative disparity indicates more "0"s than "1"s. The average disparity determines the DC component of the signals on the serial line. Running disparity is a record of the cumulative disparity of every encoded word, and is tracked by the encoder. In order to maintain neutral disparity, two different codings are defined for each data value. The 8b/10b encoder in the transmit path selects between (+) and (-) encoded word based on calculated disparity of the present data to maintain neutral disparity. In the receive path, the clock and data recovery blocks retime the incoming data and 8b/10b decoders generate 8bit data based on the received 10-bit data. A sequence of valid 8b/10b coded characters has a maximum run length of 5-bits (i.e., five consecutive "1"s or five consecutive "0"s before a mandatory bit transition). This assures adequate transitions for robust clock recovery. The recovered data is aligned on a 10-bit boundary by detecting and aligning to special characters in the incoming data stream. Data is word-aligned using the comma (/K/) character. A comma character is a special character that contains a unique pattern (0011111 or its complement 1100000) in the 10-bit space that makes it useful for delim-
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
iting word boundaries. The special characters K28.1, K28.5 and K28.7 contain this comma sequence and are treated as valid comma characters by the SERDES. The following table shows all of the valid special characters. All of the special characters are made available to the FPGA logic; however only the comma characters are used by the SERDES logic. The different codings that are possible for each data value are shown as encoded word (+) and encoded word (-). The table also illustrates the 8b/10b bit labeling convention. The bit positions of the 8-bit characters are labeled as H,G,F,E,D,C,B and A and the bit positions of the 10-bit encoded characters are labeled as a, b, c, d, e, i, f, g, h, and j. The encoded words are transmitted serially with bit 'a' transmitted first and bit 'j' transmitted last.
Table 27. Valid Special Characters
K Character K28.0 K28.1 /comma/ K28.2 K28.3 /A/ K28.4 K28.5 /comma/ K28.6 K28.7 /comma/ K23.7 K27.7 K29.7 K30.7 HGF EDCBA 765 43210 000 11100 001 11100 010 11100 011 11100 100 11100 101 11100 110 11100 111 11100 111 10111 111 11011 111 11101 111 11110 Encoded Word (-) K Control 1 1 1 1 1 1 1 1 1 1 1 1 abcdei fghj 001111 0100 001111 1001 001111 0101 001111 0011 001111 0010 001111 1010 001111 0110 001111 1000 111010 1000 110110 1000 101110 1000 011110 1000 Encoded Word (+) abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 1001 110000 0111 000101 0111 001001 0111 010001 0111 100001 0111
Transmit Path (FPGA to Backplane) Logic The transmitter section accepts four groups of either 8-bit unencoded data or 10-bit encoded data at the parallel interface to the FPGA logic. It also uses the reference clock, REFCLK[P:N] to synthesize an internal high-speed serial bit clock. The serialized transmitted data are available at the differential CML output pins to drive either an optical transmitter, coaxial media or a circuit board backplane. As shown in Figure 49, the basic blocks in the transmit path include: SERDES/FPGA Interface and 4:1 Multiplexer * Low speed parallel core/FPGA interface * 4:1 multiplexer Transmit SERDES * 8b/10b Encoder * 10:1 Multiplexer * CML Output Buffer Detailed descriptions of the logic blocks are given in following sections. Detailed descriptions of transmit clock distribution, including the transmit PLL are given in later sections of this data sheet.
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ORCA ORSPI4 Data Sheet
Figure 49. Basic Logic Blocks, Transmit Path, Single Channel (Typical Reference Clock Frequency)
Note: x= [A, B, ... D]
FPGA Logic
TWDx[31:0] TCOMMAx[3:0] TBIT9x[3:0] TSYS_CLK_x
32 4 4
Backplane Serial Link Interface and MUX Block
STBD_x[7:0] 8
8-bit data
TX SERDES Block
8B/10B Encoder (with bypass)
HDOUTP_x
STBD_x[8]
FIFO
4:1 MUX (x9)
K-control
10:1 MUX
Force-ve disparity
STBD_x[9]
CML Buffer with Preemphasis
HDOUTN_x
/4
STBC311_x
312.5 MHz
PLL
PRBS Gen.
Logic Common to Quad
REFCLKP
78.125 MHz
MUX
TCKSEL[0:1]
SERDES/FPGA Logic Interface and 4:1 Multiplexer These blocks provide the data formatting and transmit data and clock signal transfers between the SERDES and the FPGA Logic. Control and status registers in the FPGA portion of the chip control the transmit logic and record status. These bits are passed to the core using the FPGA System Bus and are described in later sections of this data sheet. The low-speed transmit interface consists of a clock and 4 data bytes, each with an accompanying control bit. The data bytes are conveyed to the MUX via the TWDx[31:0] ports (where x represents the channel label [A,B,C or D]. The control bits are TCOMMAx[3:0] which define whether the input byte is to be interpreted as data or as a special character and TBIT9x[3:0] which are used to force a negative disparity present state. The data and control signals are synchronized to the transmit clock, TSYS_CLK_x. Both the data and control are strobed into the core on the rising edge of TSYS_CLK_x. Note that each TBIT9x[3:0] controls the disparity of the encoded version of its corresponding data byte. Setting bit TBIT9C[3] to "1", for instance, will force the 8b/10b encoder to asserts a current negative running disparity state. This will cause it to encode TWDC[31:24] positively (more "1"'s than "0"'s). Setting TBIT9x to 0 will leave the encoder free to alternate between positive and negative encoding to maintain a zero running disparity. The MUX is responsible for taking 40 bits of data/control at the low-speed transmit interface and up-converting it to 10 bits of data/control at the SERDES transmit interface. The MUX has two clock domains - one based on the clock received from the SERDES block and a second that comes from the FPGA at 1/4 the frequency of the SERDES clock. The time sequence of interleaving data/control values is shown in Figure 50.
{
TCK78
From other 3 channels From Control Register
To other 3 channels
{
CML Buffer
REFCLKN
156.25 MHz
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ORCA ORSPI4 Data Sheet
Figure 50. TRANSMIT MUX Block Timing - Single Channel. (NOTE: xx = A, B, C, or D)
TWDxx[31:24], TCOMMAxx[3] TBIT9xx[3] TWDxx[23:16], TCOMMAxx[2] TBIT9xx[2] TWDxx[15:8], TCOMMAxx[1] TBIT9xx[1] TWDxx[7:0], TCOMMAxx[0] TBIT9xx[0]
p7-0 p8
p9
t7-0
t8
t9
q7-0 q8
q9
x7-0 x8
x9
r7-0
r8
r9
y7-0 y8
y9
s7-0 s8
s9
z7-0 z8
z9
LATENCY = 4 TSYS_CLK_xx CLOCKS
10-bit wide data p q r s t x y z
STBDxx[9:0]
TSYS_CLK_xx
SERDES Block The SERDES block accepts either 8-bit data to be encoded or 10-bit unencoded data at the parallel input port from the MUX/DEMUX block. It also accepts the reference clock at the REFCLK input and uses this clock to synthesize the internal high-speed serial bit clock. The internal STBC311x clock is derived from the reference clock. The frequency of this clock depends on the setting of the half-rate/full-rate control bit setting the mode of the SERDES and the frequency of the REFCLK and/or that of the high-speed serial data. A falling edge on the STBC311x clock port will cause a new data character to be transferred into the SERDES block. The latency from the SERDES block input to the high-speed serial output is five STBC311x clock cycles, as shown in Figure 51.
Figure 51. Transmit Path Timing - Single SERDES Channel (NOTE: xx = A, B, C, or D)
STBDxx[9:0] p q r s t x y z
STBC311xx
LATENCY = 5 STBC311x CLOCKS HDOUT_xx
pppp pppppp 0123 456789
Each block also sends a clock to the FPGA logic. This clock, TCK78[A,B], is sourced from one of the four MUX blocks and has the same frequency as TSYS_CLK_x, but arbitrary phase. Within each MUX block, the low frequency clock output is obtained by dividing by four, the SERDES STBC311x clock, which is used internally to synchronize the transmit data words. TCKSEL control bits select the channel to source TCK78. The internal signals STBDx[9:0] (where x is represents A, B, C or D) from the MUX block carry unencoded character data and control bits. The 10th bit (STBDx[9]) of each data lane into the SERDES is used to force a negative disparity present state. 109
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ORCA ORSPI4 Data Sheet
8b/10b Encoder and 1:10 Multiplexer The 8b/10b encoder encodes the incoming 8-bit data into a 10-bit format as described previously. The input signals to the block, STBDx[7:0] are used for the 8-bit unencoded data. STBDx[8] is used as the K_control input to indicate whether the 8 data bits need to be encoded as special characters (K_control = "1") or as data characters (K_control = 0). When STBDx[9:0] = "1", a negative disparity present state is forced. When the encoder is bypassed STBDx[9:0] serve as the data bits for the 10-bit unencoded data. Within the 8b/10b transmission code, the bit positions of the 10-bit encoded transmission characters are labeled as a, b, c, d, e, i, f, g, h, and j in that order. Bit a corresponds to STBDx[0], bit b to STBDx[1], bit c to STBDx[2], bit d to STBDx[3], bit e to STBDx[4], bit i to STBDx[5], bit f to STBDx[6], bit g to STBDx[7], bit h to STBDx[8], and bit j to STBDx[9]. The 10-bit wide parallel data is converted to serial data by the 10:1 Multiplexer. The serial data are then sent to the CML output buffer and are transmitted serially with STBDx[0] transmitted first and STBDx[9] transmitted last. CML Output Buffer The transmitter's CML output buffer is terminated on-chip in 86 ohms to optimize the data eye, as well as to reduce the number of discrete components required. The differential output swing reaches a maximum of 1.2 V PP in the normal amplitude mode. A half amplitude mode can be selected via configuration register bit HAMP_x. Half amplitude mode can be used to reduce power dissipation when the transmission medium has minimal attenuation or for testing of the integrity (loss) of the physical medium. A programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maximize the data eye opening at the far-end receiver. Preemphasis is particularly useful when the data are transmitted over backplanes or low-quality coax cables which have a frequency-dependent amplitude loss. For example, for FR4 material at 2.5 GHz, the attenuation compared to the 1.0 GHz value is about 3 dB. The attenuation is a result of skin effect loss of the PCB conductor and the dielectric loss of the PCB substrate. This attenuation causes intersymbol interface which results in the closing of the data eye opening at the receiver. Since this effect is predictable for a given type of PCB material, it is possible to compensate for this effect in two ways - transmitter preemphasis and receiver equalization. Each of these techniques boosts the high frequency components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better power utilization. It also gives a better signal-to-noise ratio because receiver equalization amplifies both the signal and the noise at the receiver Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also degrade the data eye opening at the receiver. In the ORSPI4 the degree of transmit preemphasis can be programmed with a two-bit control from the microprocessor interface as shown in Table 28. The high-pass transfer function of the preemphasis circuit is given by the following equation, where the value of "a" is shown in Table 28. H(z) = (1 - az -1) (1)
Table 28. Preemphasis Settings
PE1 0 0 1 1 PE0 0 1 0 1 12.5% 12.5% 25% Amount of Preemphasis (a) 0% (No Preemphasis)
Receive Path (Backplane to FPGA) Logic The receiver section receives high-speed serial data at the external differential CML input pins. These data are fed to the clock recovery section which generates a recovered clock and retimes the data. Therefore the receive clocks are asynchronous between channels. The retimed data are deserialized and presented as an 8-bit decoded or a 10-bit unencoded parallel data on the output port. The receiver also optionally recognizes comma characters, detects code violations and aligns the bit stream to the proper word boundary.
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As shown in Figure 52, the basic blocks in the receive path include: Receive SERDES Block * CML input buffer * Receive PLL * 1:10 demultiplexer (DEMUX) * Clock and Data Recovery (CDR) section * 10b/8b decoder * 1:4 demultiplexer and SERDES/FPGA interface * 1:4 DEMUX * Low speed parallel SERDES/FPGA logic interface * Multi-channel alignment logic
ORCA ORSPI4 Data Sheet
Figure 52. Basic Logic Blocks, Receive Path, Single Channel (Typical Reference Clock Frequency)
CV_SELx RWBIT9x[3:0] MRWDx[39:0]
40
Note: x= [A, ..., B] x# = [1, 2] SBYTSYNC_x
2:1 MUX (x40)
4
Fibre Channel State Machine
SWDSYNC_x
RSYS_CLK_#
78.125 MHz
32-bit data 36 4 bits k-ctrl Synchronization Status bits
FIFO
3 10 32 4 4
RWDx[31:0]
32-bit data
SRBD_x[0:9]
FPGA Logic
MultiRWBIT8x[3:0] Channel 4 bits k-control Alignment RALIGNx[3:0]
78.125 MHz Clock
1:4 DEMUX (x 10)
SCVx
8B/10B Encoder Byte 1:10 CML (with Align DEMUX Buffer bypass) CDR PLL PRBS Checker RX SERDES Block
HDINP_x
HDIN_x
Align Character Detect
312.5 MHz Clocks 2
RWCKx
78.125 MHz
Multi-Channel Alignment Block
XAUI State Machine
DEMUX Block
Backplane Serial Link
Logic Common to Quad
REFCLKP
78.125 MHz
MUX
RCKSEL[0:1]
Each channel provides its own received clock, received data and K-character detect signals to the FPGA logic. Incoming data from multiple channels can be aligned using comma (/K/) characters or /A/ character (as specified either in Fibre Channel specifications or in IEEE 802.3ae for XAUI based interfaces). If the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in this 8b/10b bypass mode.
{
RCK78
From other 3 channels From Control Register
To other 3 channels
{
REFCLK Buffer
REFCLKN
156.25 MHz
111
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ORCA ORSPI4 Data Sheet
Synchronization The ORSPI4 SERDES RX logic performs four levels of synchronization on the incoming serial data stream. Each level builds upon the previous, providing first bit, then byte (character), then channel (32-bit word), and finally multichannel alignment. Bit alignment is the task of the Clock/Data Recovery (CDR) block. This block utilizes a PLL that locks to the transitions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. If the PLL is unable to lock to the serial data stream, it instead locks to REFCLK to stabilize the Voltage-Controlled Oscillator (VCO), and periodically switches back to the serial data stream to again attempt synchronization. This process continues until a valid input data stream is detected and lock is achieved. The CDR can maintain lock on data as long as the input data stream contains an adequate data "eye" (i.e., jitter is within specification) and the maximum data stream run length is not exceeded. Byte alignment occurs once valid bit alignment is achieved. The byte aligner looks for a particular 7-bit sequence (either 0011111 or its complement, 1100000) that, has been 8b/10b encoded per Fibre Channel or IEEE 802.3.2002 specifications, only occurs in the comma (/K/) characters K28.1, K28.5 and K28.7. Byte alignment only occurs when the ENBYSYNC_x signal for that channel is active high, and re-alignment occurs on each 7-bit sequence encountered. However, if ENBYSYNC_x is asserted active high and no comma character is encountered, and then is brought inactive low, the channel will still perform one byte alignment operation on the next comma character. Byte alignment occurs immediately when an alignment sequence is detected, so the lock time is only one clock period. Word (32-bit) alignment can occur after the Fibre Channel (XAUI_MODE_x = "0") or XAUI (XAUI_MODE_x = "1") state machine has reached the in-synchronization state. In Fibre Channel mode, synchronization (WDSYNC_x = "1") will occur after three ordered sets of data have been received in the absence of any code violations. After this, the next ordered set will cause the output data to be aligned such that the comma character is in the most significant byte. Thus, 32-bit word alignment has been achieved when four ordered sets have been detected. The time required is directly dependent on comma-character density. Once word alignment is accomplished, no further alignment occurs unless and until WDSYNC_x goes to zero and back to one again. Comma characters that are not located in the most significant byte position will not trigger further re-alignment while WDSYNC_x is active. This behavior is as defined by the Fibre Channel specification. However, it means that, if the channel experiences an abrupt delay change (as could occur if an external mux performs protection switch between two links) and if the delay change is close enough to a full character or characters that not enough code violations are generated to cause loss of WDSYNC_x, the channel could become misaligned and remain that way indefinitely. As mentioned above, this behavior is that defined by the Fibre Channel specification. In XAUI mode, as the state diagram later in this data sheet indicates, three error-free code-groups containing commas must be detected before synchronization is declared. Multi (2 or 4) channel alignment (Lane alignment in XAUI mode) can be performed after 32-bit word alignment is complete. Multi-channel alignment is described in later sections of this data sheet. Receive CML Input Buffer and SERDES The receiver section receives high-speed serial data at its differential CML input port. The receive input is an AC coupled input. The received data is sent to the clock recovery section which generates a recovered clock and retimes the data. Valid data will be received after the receive PLL has locked to the input data frequency and phase. The received serial data is converted to a 10-bit wide parallel data by the 1:10 demultiplexer. Clock recovery is performed by the SERDES block for each of the eight receive channels. This recovered data is then aligned to a 10-bit word boundary by detecting and aligning to a comma special character. Word alignment is done for either polarity of the comma character. The 10-bit code word is passed to the 8b/10b decoder, which provides an 8-bit byte of data, a special character indicator bit and a SBYTSYNC_x signal (where again x is a placeholder for A,...,D). Data from a SERDES channel is sent to the DEMUX block in 10-bit raw form or 8-bit decoded form. Accompanying this data are the comma-character indicator (SBYTSYNC_x), link-state indicator (SWDSYNC_x), clocks (SRBC0_x, and SRBC1_x), and code-violation indicator (SCVx). The two internal clocks operated at twice the reference clock
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ORCA ORSPI4 Data Sheet
frequency. With the 8b10bR_x control bit of the SERDES channel set to "1", the data presented at SRBD_x[9:0] will be decoded characters. Bit 8 will indicate whether SRBDx[7:0] represents an ordinary data character (bit 8 = 0), or whether SRBD_x[7:0] represents a special character, like a comma. Bit 9 may be either a code violation indicator or one of seven out of synchronization state indicators, as described later.
Figure 53. Receive Path Timing for a Single SERDES Channel. (NOTE: xx = A, B, C, or D)
1-bit
EMBEDDED CORE
HDINx
pppp pppppp q 0123 456789 0
.....
.....
X
r
2
r
3
r
4
r
5
r
6
r
7
r
8
r
9
sssss 01234
.....
LATENCY = APPROX 23 CLOCKS SRBDX[9:0]
10-bit
P
SRBDX[9:0] SRBC0X SRBC1X SBYTSYNCX, SVCX SWDSYNCX
.....
P
Q
R
S
T
Y
Z
..... ..... ..... ..... .....
When 8b10bR is set to "0", the data at SRBD_x[9:0] will not be decoded. The XAUI link-state machine should not be used in this mode of operation. When in XAUI mode, the MUX/DEMUX looks for /A/ (as defined in IEEE 802.3ae v.2.1) characters for channel alignment and requires the characters to be in decoded form for this to work 1:4 Demultiplexer (DEMUX) The 1:4 DEMUX has to accumulate four sets of characters presented to it at the SERDES receive interface and put these out at one time at the low-speed receive interface. Another task of the 1:4 DEMUX is to recognize the synchronizing event and adjust the 4-byte boundary so that the synchronizing character leads off a new 4-byte word. In Fibre Channel mode, this synchronizing character is a comma. This feature will be referred to as DEMUX word alignment in other areas of this document. DEMUX word alignment will only occur when the communication channel is synchronized. When there is no synchronization of the link, the 1:4 DEMUX will continue to output 4-byte words at some arbitrary, but constant, boundary. There are 2 control register bits available for each channel for word alignment. They are DOWDALGN_x and NOWDALGN_x. The DOWDALGN_x bit is positive edge triggered. Writing a 0 followed by a "1" to this register bit will cause the corresponding DEMUX to look for a new comma character and align the 32-bit word such that the comma is in the most significant byte position. It is important that the comma is in the most significant byte position since the multichannel aligner looks for comma in the most significant byte only. Typically, it is not necessary to set the DOWDALGN_x bit. When the link state machine loses synchronization (DEMUXWAS_x register bit is 0), the DEMUX block automatically looks for a new comma character irrespective of whether the DOWDALGN_x bit is set or not. However, as discussed earlier, the comma character may become misaligned without the Fibre Channel link state machine indicating a loss of synchronization. In such cases, the DOWDALGN_x bit must be toggled to force resynchronization.
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ORCA ORSPI4 Data Sheet
The NOWDALGN_x bit is a level-sensitive bit. If it is a "1", then the DEMUX does not dynamically alter the word boundary based on comma and SWDSYNC_x output of the SERDES. This might be useful if a channel were configured to bypass the multi-channel alignment FIFO and raw 40-bits of data are directed from SERDES to FPGA. In Fibre Channel mode, the default setting (NOWDALGN_x = 0) causes the word boundary to be set as soon as the SERDES SWDSYNC_x output is a "1" and a comma character has been detected. The character that is the comma becomes the most-significant portion of the demultiplexed word. When the SERDES loses link synchronization it will drop SWDSYNC_x low. The DEMUX will begin search for word alignment as soon as SWDSYNC_x goes to "1" again. The DEMUX passes on to the channel alignment FIFO block a set of control signals that indicate the location of the synchronizing event. RALIGN_x[3:0] are these indicators. If there is no link synchronization, all of the RALIGN_x[[3:0] bits will be zeros independent of synchronizing events that come in. When the link is synchronized, then the bit that corresponds to the time of the synchronization event will be set to a "1". The relationship between a time sequence of values input at SRBDx[7:0] to the values output at RWD_x[39:0] is shown in Figure 54. A parallel relationship exists between SRBDx[8] and RWBIT8_x[3:0] as well as between SRBD_x[9] and RWBIT9_x[3:0].
Figure 54. Receive DEMUX Block for a Single SERDES Channel. (NOTE: xx = A, B, C, or D)
10-bit SRBDxx[9:0] p p p p p p p p
LATENCY = 4 RSYS_CLK [A1,...,B2] CLOCKS RWD_XX[31:24] RWBIT8_XX[3] RWBIT9_XX[3] RWD_XX[23:16] RWBIT8_XX[2] RWBIT9_XX[2] RWD_XX[15:8] RWBIT8_XX[1] RWBIT9_XX[1] RWD_XX[7:0] RWBIT8_XX[0] RWBIT9_XX[0] p
40-bit pp 89 t tt 7-0 8 9
7-0
q
7-0
qq 89
x
xx 7-0 8 9
r
rr 7-0 8 9
y
yy 7-0 8 9
s
ss 7-0 8 9
z
zz 7-0 8 9
One clock per block of two or four channels, called RCK78, is sent to the FPGA. The control bits RCKSEL[A,B] are used to select the channel that is the source for these clocks. Link State Machines Two link state machines are included in each SERDES channel; one for XAUI applications and a second for Fibre Channel applications. The Fibre Channel link state machine is responsible for establishing a valid link between the transmitter and the receiver and for maintaining link synchronization. The machine is initially in the loss of synchronization (LOS) state upon power-on reset. This is indicated by WDSYNC_x = 0. While in this state, the machine looks for a particular number of consecutive idle ordered sets without any invalid data transmission in between before declaring synchronization achieved. Achievement of synchronization is indicated by asserting WDSYNC_x = "1". Specifically, the machine looks for three continuous idle ordered sets without any misaligned comma character or any running disparity based code violation in between. In the event of any such code violation, the machine would reset itself to the
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ORCA ORSPI4 Data Sheet
ground state and start its search for the idle ordered sets again. A typical valid sequence for achieving link synchronization would be K28.5 D21.4 D21.5 D21.5 repeated three times. In the synchronization achieved state, the machine constantly monitors the received data and looks for any kind of code violation that might result due to running disparity errors. If it were to receive four such consecutive invalid words, the link machine loses its synchronization and once again enters the loss of synchronization state (LOS). A pair of valid words received by the machine overcomes the effect of a previously encountered code violation. LOS is indicated by the status of WDSYNC_x output which now transitions from "1" to "0". LOS is also indicated by DEMUXWAS_x status register bit. This bit is set to "0" during loss of synchronization. At this point the machine attempts to establish the link yet again. Figure 55 shows the state diagram for the Fibre Channel link state machine.
Figure 55. Fibre Channel Link State Machine State Diagram
LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1) VW CV a 2 VW OS CV h LOSS OF SYNCHRONIZATION (WDSYNC_X = 0) OS CV g CV b 2 VW 1VW CV c 2 VW 1VW CV d 1VW
OS LOS = 1 f RST
LSM_ENABLE
e
+
POWERUP_RESET
OS LAST ORDERED SET RECEIVED: OS: IDLE ORDERED SET (A 4 CHARACTER BASED WORD HAVING COMMA AS THE 1ST CHARACTER) VW: VALID WORD (A 4 CHARACTER BASED WORD HAVING NO CODE VIOLATION) WITH AT LEAST TWO PRECEEDING VALID WORDS CV: CODE VIOLATION (RUNNING DISPARITY BASED ON ILLEGAL COMMA POSITION) 1VW: FIRST VALID WORD AFTER A CODE VIOLATION 2VW: SECOND VALID WORD AFTER A CODE VIOLATION
XAUI Link Synchronization Function For each lane, the receive section of the XAUI link state machine incorporates a synchronization state machine that monitors the status of the 10-bit alignment. A 10-bit alignment is done in the SERDES based on a comma character such as K28.5. A comma (0011111 or its complement 1100000) is a unique pattern in the 10-bit space that cannot appear across the boundary between any two valid 10-bit code-groups. This property makes the comma useful for delimiting code-groups in a serial stream. This mechanism incorporates a hysteresis to prevent false synchronization and loss of synchronization due to infrequent bit errors. For each lane, the sync_complete signal is disabled until the lane achieves synchronization. The synchronization state diagram is shown in Figure 56. The XAUI state machine does not have any control over the SERDES byte aligner. It is the user's responsibility to control the byte aligner through software access of register map address 30800.
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ORCA ORSPI4 Data Sheet
This state machine is modeled after draft IEEE 802.3ae, version 2.1 but will also operate properly with version 4.1 implementations. Table 29 and Table 30 describe the state variables used in Figure 56. Note that it takes four idle ordered sets (ex: k28.5, Dx.y, Dx.y, Dx.y) to bring the state machine from a loss-of-sync to a sync_acq'd_1 state. Instead, when back-to-back commas are used, it takes a total of five commas to achieve the same result as with idle ordered sets.
Table 29. XAUI Link Synchronization State Diagram Notation--Variables
Variable sync_status Description FAIL: Lane is not synchronized (correct 10-bit alignment has not been established). OK: Lane is synchronized. OK_NOC: Lane is synchronized but a comma character has not been detected in the past 200 code-groups. TRUE: Align subsequent 10-bit words to the boundary indicated by the next received comma. FALSE: Maintain current 10-bit alignment. Current number of consecutive cg_good indications.
enable_CDET gd_cg
Table 30. XAUI Link Synchronization State Diagram--Functions
Function sync_complete cg_comma cg_good cg_bad no_comma Description Indication that alignment code-group alignment has been established at the boundary indicated by the most recently received comma. Indication that a valid code-group, with correct running disparity, containing a comma has been received. Indication that a valid code-group with the correct running disparity has been received. Indication that an invalid code-group has been received. Indication that comma timer has expired. The timer is initialized upon receipt of a comma.
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Figure 56. XAUI Link Synchronization State Diagram
reset
ORCA ORSPI4 Data Sheet
Loss_of_Sync sync_status <=FAIL enable_CDET <= TRUE sync_complete Comma_Detect_1 enable_CDET <= FALSE cg_bad cg_comma Comma_Detect_2
cg_bad
cg_comma Comma_Detect_3
cg_bad cg_comma
Sync_Aqc'd_1 sync_status <= OK no_comma and cg_bad cg_bad no_comma and cg_bad Sync_Aqc'd_2 gd_cg <= 0 cg_good cg_bad Sync_Aqc'd_3 gd_cg <= 0 cg_good cg_bad Sync_Aqc'd_4 gd_cg <= 0 cg_good cg_bad cg_good x (gd_cg = 3) cg_good*(gd_cg=3)
Sync_Aqc'd_1a sync_status <= OK_NOC
cg_comma Sync_Aqc'd_2a gd_cg <= gd_cg + 1 cg_good x (gd_cg ! = 3) cg_bad cg_good x (gd_cg = 3) Sync_Aqc'd_3a gd_cg <=gd_cg + 1 cg_bad Sync_Aqc'd_4a gd_cg <=gd_cg + 1 cg_bad cg_good x (gd_cg ! = 3) cg_good x (gd_cg ! = 3)
Reference Clock Requirements There is one pair of SERDES reference clock inputs on the ORSPI4. The differential reference clock is distributed to all channels in the block. Each channel has a differential buffer to isolate the clock from the other channels. The input clock is preferably a differential signal; however, the device can operate with a single-ended input. The input reference clock directly impacts the transmit data eye, so the clock should have low jitter. In particular, jitter compo117
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
nents in the DC to 5 MHz range should be minimized. The required electrical characteristics for the reference clock are given in Table 71. Note: In sections of this data sheet, the differential clocks are simply referred to as the reference clock as REFCLK. Synthesized and Recovered Clocks The SERDES block contains its own dedicated PLLs for transmit and receive clock generation. The user provides a reference clock of the appropriate frequency, as described in the previous section. The transmitter PLL uses the REFCLK inputs to synthesize the internal high-speed serial bit clocks. The receiver PLLs extract the clock from the serial input data and retime the data with the recovered clock. The receive PLL for each channel has two modes of operation - lock to reference and lock to data with retiming. When no data or invalid data is present on the HDINP_x and HDINN_x pins, the receive VCO will not lock to data and its frequency can drift outside of the nominal 350 ppm range. Under this condition, the receive PLL will lock to REFCLK for a fixed time interval and then will attempt to lock to receive data. The process of attempting to lock to data, then locking to clock will repeat until valid input data exists. There is also a control register bit per channel to force the receive PLL to always lock to the reference clock. The high-speed transmit and receive serial data links can run at 0.6 to 3.7 Gbits/s, depending on the frequency of the reference clock and the state of the control bits from the internal transmit control register. The interface to the serializer/deserializer block runs at 1/10th the bit rate of the data lane. Additionally, the MUX/DEMUX logic converts the data rate and bit-width so the FPGA core can run at 1/4th this frequency, which gives a range of 15 to 92.5 MHz for the data in and out of the FPGA. Internal Clock Signals at the FPGA/Core SERDES Interface There are several clock signals defined at the FPGA/SERDES interface in addition to the external reference clock. All of the SERDES clock signals are shown in Figure 57 and are described following the paragraphs.
Figure 57. SERDES Clock Signals (High-Speed Serial I/O Also Shown)
RCK78 TCK78 RWCKA RSYS_CLK_1 TSYS_CLK_A RWCKB 2 2
Common Logic Channel A
REFCLK[P:N] HDIN[P:N] HDOUT[P:N] HDIN[P:N] HDOUT[P:N] HDIN[P:N] HDOUT[P:N] HDIN[P:N] HDOUT[P:N]
2 2
Channel B
TSYS_CLK_B RWCKC
2 2
Channel C
TSYS_CLK_C RWCKD RSYS_CLK_2 TSYS_CLK_D
2 2 2
Channel D
REFCLKP, REFCLKN: These are the differential reference clocks provided to the ORSPI4 device as described earlier. They are used as the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbits/s, the reference clocks will be at a frequency of 156.25 MHz. RWCK[A:D]: These are the low-speed receive clocks from the SERDES to the FPGA across the core-FPGA interface.
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ORCA ORSPI4 Data Sheet
These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCK_A belongs to Channel A, RWCK_B belongs to channel B and so on. With a reference clock input of 156.25 MHz, these clocks operate at 78.125 MHz. RCK78: These are muxed outputs of RWCKA[A:D] and RWCKB[B:D] respectively. With a reference clock input of 156.25 MHz, these clocks operate at 78.125 MHz. RSYS_CLK_[1:2] These clocks are inputs to the SERDES. These are used by each channel as the read clock to read received data from the alignment FIFO within the SERDES. To guarantee that there is no overflow in the alignment FIFO, it is an absolute requirement that the write and read clocks be frequency locked to 0 ppm. Examples of how to achieve this are shown in the section on recommended board-level clocking. TCK78: This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the four transmit SERDES clocks operating at up to 92.5 MHz in the SERDES. TSYS_CLK[A:D]: These clocks are inputs to the SERDES from the FPGA. These are used by each channel to control the timing of the Transmit Data Path. To guarantee correct transmit operation, these clocks must be frequency locked within 0 ppm to TCK78.
List of Operating Modes SERDES
Transmit and Receive Clock Rates Table 31 shows typical relationship between the data rates, the reference clock, the transmit TCK78 clock and the receive RCK78 clock. The selection of full-rate or half-rate for a given reference clock speed is set by bits in the transmit and receive control registers, and can be set on a per-channel basis.
Table 31. Transmit Data and Clock Rates
TCK78[A: B] and RCK78[A:B] Clocks 15 MHz 25 MHz 31.25 MHz 50 MHz 62.5 MHz 78 MHz 92.5 MHz Rate of Channel Selected as Clock Source Half Half Half Full Full Full Full
Data Rate 0.6 Gbits/s 1.0 Gbits/s 1.25 Gbits/s 2.0 Gbits/s 2.5 Gbits/s 3.125 Gbits/s 3.7 Gbits/s
Reference Clock 60 MHz 100 MHz 125 MHz 100 MHz 125 MHz 156 MHz 185 MHz
Mixing Half-rate, Full-rate Modes When channel alignment is enabled, all receive channels within an alignment group should be configured at the same rate. For example, channels A and B, can be configured for twin alignment and full-rate mode, while channels C and D can be configured for half-rate mode. In quad alignment mode, all four channels must be configured in either half or full-rate mode. Register settings for multi-channel alignment are described in a later section. Besides taking in a TSYS_CLK_x from the FPGA logic for each channel, the transmit path logic sends back a clock of the same frequency, but arbitrary phase. This clock, TCK78, is derived from the MUX block of one of the 2 channels in its SERDES block. The MUX blocks provide the potential source for TCK78 by a divide-by-4 of the SERDES STBC311xs clock used in synchronizing the transmit data words in the STBC311x clock domain. The STBC311x clocks are internal to the core and are not brought across the core/FPGA interface
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ORCA ORSPI4 Data Sheet
The receiver section receives high-speed serial data at its differential CML input port and sends it in to the Clock and Data Recovery (CDR) block. The CDR block then generates a recovered clock (RWCKx) and retimes the data. Thus, the recovered receive clocks are asynchronous between channels. Transmit Clock Source Selection The TCKSEL[A:B] bit select the source channel of TCK78. The selection of the source for TCK78 is controlled by this bit as shown in Table 32.
Table 32. TCK78 Source Selection
TCKSEL0 0 1 0 1 TCKSEL1 0 0 1 1 Clock Source Channel A Channel B Channel C Channel C
Recommended Transmit Clock Distribution for the ORSPI4 As an example of the recommended clock distribution approach, TSYS_CLK_[A:D] can be sourced by TCK78 as shown in Figure 58 if the transmit line rate are common for all four channels in a quad.
Figure 58. Transmit Clocking for a Single Block
TCK78 TSYS_CLK_A
Common Logic Channel A
2
REFCLK[P:N]
156.25 MHz
FPGA Logic
TSYS_CLK_B
Channel B
Four Channels of 3.125 Gbits/s Outgoing Serial Data
TSYS_CLK_C
Channel C
TSYS_CLK_D
Channel D
All Clocks at 78.125 MHz
If the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in Figure 59 can be used. The figure shows TSYS_CLK_A and TSYS_CLK_B being sourced by TCK78 and TSYS_CLK_C and TSYS_CLK_D being sourced by TCK78/2 (the division is done in FPGA logic). Similar clocking would be used for Quad B.
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Figure 59. Mixed Rate Transmit Clocking for a Single Block
TCK78 Channel A Selected as Clock Source TSYS_CLK_A
ORCA ORSPI4 Data Sheet
50 MHz
Common Logic Channel A
2
REFCLK[P:N]
100 MHz
FPGA Logic
TSYS_CLK_B
Channel B
Two Channels of 2.0 Gbits/s (Full-Rate) Outgoing Serial Data
/2
TSYS_CLK_C
Channel C
TSYS_CLK_D 25 MHz
Channel D
Two Channels of 1.0 Gbits/s (Half-Rate) Outgoing Serial Data
Receive Clock Source Selection and Recommended Clock Distribution In the receive path, one clock per bank of four channels, called RCK78, is sent to the FPGA logic. The control register bits RCKSEL[0:1] are used to select the clock source for these clocks. The selection of the source for RCK78 is controlled by these bits as shown in Table 33.
Table 33. RCK78 Source Selection
RCKSEL0 0 1 0 1 RCKSEL1 0 0 1 1 Clock Source Channel A Channel B Channel C Channel C
In the receive channel alignment bypass mode, the data and recovered clocks for the four channels are independent. The data for each channel are synchronized to the recovered clock from that channel.
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Figure 60. Receive Clocking for a Single Quad
78.125 MHz
ORCA ORSPI4 Data Sheet
RCK78 RWCKA
Common Logic Channel A
2
REFCLK[P:N]
156.25 MHz
FPGA Logic
RSYS_CLK_1 RWCKB
Channel B
All Recovered Clocks at 78.125 MHZ
RWCKC
Channel C
Four Channels of 3.125 Gbits/s Incoming Serial Data
RWCKD
Channel D
RSYS_CLK_2
Figure 61. Receive Clocking for Mixed Line Rates
25 MHz or 50 MHz RCK78 RWCKA
Common Logic Channel A
2
REFCLK[P:N]
100 MHz
Two Channels of 2.0 Gbits/s (Full-Rate) Incoming Serial Data
Recovered Clocks at 50 MHZ
RSYS_CLK_1 RWCKB
FPGA Logic
RWCKC
Channel B
Channel C
Recovered Clocks at 25 MHZ
RWCKD
Channel D
RSYS_CLK_2
Two Channels of 1.0 Gbits/s (Half-Rate) Incoming Serial Data
Multichannel Alignment The alignment FIFO allows the transfer of all data to the system clock. The Multi-Channel Alignment block (Figure 52) allows the system to be configured to allow the frame alignment of multiple, slightly varying, data streams. This optional alignment ensures that matching SERDES streams will arrive at the FPGA in perfect data synchronization. Each channel is provided with a 24 word x 36-bit FIFO. The FIFO can perform two tasks: (1) to change the clock domain from receive clock to a clock on the FPGA side, and (2) to align the receive data over 2, 4, or 8 channels. This FIFO allows a timing budget of +/- 230.4 ns that can be allocated to skew between the data lanes and for transfer to the system clock. The input to the FIFO consists of 36-bits of demultiplexed data, RALIGN_x[3:0], RWD_x[31:0], and RWBIT8_x[3:0]. The four RALIGN_x bits are control signals, and can be the alignment character detect signals, indicating the presence of a comma character in Fibre Channel mode and the /A/ character in XAUI mode. The other 32 RWD_x bits are the 8-bit data bytes from the 8b/10b decoder. The alignment character, if present, is the MSB of the data. The 122
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
RWBIT8_x indicates the presence of a Km.n control character in the receive data byte. Only RWBIT8_x and RWD_x inputs are stored in the FIFO. During alignment process, RALIGN[3]_x is used to synchronize multiple channels. If a channel is not in any alignment group, it will set the FIFO-write-address to the beginning of the FIFO, and will set the FIFO-read-address to the middle of the FIFO, at the first assertion of RALIGN[3]_x after reset or after the resync command. The ORSPI4 has a total of four SERDES channels. The incoming data of these channels can be synchronized in several ways or can be independent of one another. Two SERDES channels can be aligned together. Channel A and B and/or channel C and D can form a pair as shown in Figure 62. Alternately, all four SERDES channels can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s as shown in Figure 63. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels.
Figure 62. Twin Channel Alignment
Channel A Channel B Channel C Channel D
Channel A Channel B Channel C Channel D
Twin alignment of channels A and B
t1 t0
Twin alignment of channels C and D
Figure 63. Alignment of SERDES Quad (4-Channels)
Channel A Channel B Channel C Channel D Channel A Channel B Channel C Channel D t0
Quad alignment of channels A. B, C and D
For every alignment group, there are both an OVFL and an OOS status register bit. The OVFL bit is set when alignment FIFO overflow occurs. The OOS bit is flagged when the down counter in the synchronization algorithm has reached a value of 0 and alignment characters from all channels within an alignment group have not been received. XAUI Lane Alignment Function (Lane Deskew) In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The mechanism restores the timing relationship between the four lanes by lining up the /A/ characters into a column. Figure 64 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies that at least 80 bits of skew compensation capability should be provided, which the ORSPI4 significantly exceeds.
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Figure 64. Deskew Lanes by Aligning /A/ Columns
LANE 0 K R R K K R R R R K K K R R R A K K R R R A K K K R R K A K K R R K A K K R R R K K K R R R K K K R R R K K R
ORCA ORSPI4 Data Sheet
LANE 1 LANE 2 K
K
LANE 3
R
R
K
LANE 0 LANE 1 LANE 2 LANE 3
K K K K
R R R R
R R R R
K K K K
R R R R
K K K K
A A A A
R R R R
K K K K
K K K K
R R R R
K K K K
R R R R
R R R R
K K K K
SERDES/FPGA Interface This block provides the data formatting and receive data and clock signal transfers between the SERDES and the FPGA Logic. There are also control and status registers in the FPGA portion of the chip, which contain bits to control the receive logic and to record status. These are described in later sections of this Data Sheet and communicate with the core using the System Bus. The demultiplexed, receive word outputs to the FPGA are shown in Figure 52. These are each 40 bits wide. There are four of these interfaces, one for each SERDES channel. Each consist of four groups of 10-bit data or four groups of decoded information depending on setting of 8b10bR_x control register bits. Each 10-bit group of decoded information includes 8 bits of data and a one-bit K_CTRL indicator derived from the received data, and a tenth bit of status information. The function of the tenth bit varies from group to group and includes code violation, out of synchronization (OOS) indicators and the CH248_SYNC_x status bit. CH248_SYNC_x indicates the status of multi-channel alignment of channel x and is high when the count for the multi-channel alignment block reaches zero, regardless of whether or not multi-channel alignment is successful. The mapping of the 10-bit groups to the MRWD_x[39:0] bits output to the FPGA logic is summarized in Table 34 and Table 35. The various functions of the bits that vary from channel to channel, i.e., bits 29 and 19, are also described in Table 35.
Table 34. Definition of Bits of MRWDx[39:0]
8b10bR=0 Bit Index 39 38 37 36 35 34 33 32 31 30 29 28 27 26 NOCHALGN[A:B]=1 CV_SELx=0 bit 9 of 10-bit data 3 bit 8 of 10-bit data 3 bit 7 of 10-bit data 3 bit 6 of 10-bit data 3 bit 5 of 10-bit data 3 bit 4 of 10-bit data 3 bit 3 of 10-bit data 3 bit 2 of 10-bit data 3 bit 1 of 10-bit data 3 bit 0 of 10-bit data 3 bit 9 of 10-bit data 2 bit 8 of 10-bit data 2 bit 7 of 10-bit data 2 bit 6 of 10-bit data 2 8b10bR=1 NOCHALGN[A:B]=1 CV_SELx=1 CV_A3, code violation, byte 3 K_CTRL for byte 3 bit 7 of byte3 bit 6 of byte 3 bit 5 of byte 3 bit 4 of byte 3 bit 3 of byte 3 bit 2 of byte 3 bit 1 of byte 3 bit 0 of byte 3 CV_A2, code violation, byte 2 K_CTRL for byte 2 bit 7 of byte 2 bit 6 of byte 2 NOCHALGN[A:B]=0 CV_SELx=1 CH24_SYNCx K_CTRL for byte 3 bit 7 of byte3 bit 6 of byte 3 bit 5 of byte 3 bit 4 of byte 3 bit 3 of byte 3 bit 2 of byte 3 bit 1 of byte 3 bit 0 of byte 3 See Table 35 K_CTRL for byte 2 bit 7 of byte 2 bit 6 of byte 2
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8b10bR=0 Bit Index 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 NOCHALGN[A:B]=1 CV_SELx=0 bit 5 of 10-bit data 2 bit 4 of 10-bit data 2 bit 3 of 10-bit data 2 bit 2 of 10-bit data 2 bit 1of 10-bit data 2 bit 0 of 10-bit data 2 bit 9 of 10-bit data 1 bit 8 of 10-bit data 1 bit 7 of 10-bit data 1 bit 6 of 10-bit data 1 bit 5 of 10-bit data 1 bit 4 of 10-bit data 1 bit 3 of 10-bit data 1 bit 2 of 10-bit data 1 bit 1 of 10-bit data 1 bit 0 of 10-bit data 1 bit 9 of 10-bit data 0 bit 8 of 10-bit data 0 bit 7 of 10-bit data 0 bit 6 of 10-bit data 0 bit 5 of 10-bit data 0 bit 4 of 10-bit data 0 bit 3 of 10-bit data 0 bit 2 of 10-bit data 0 bit 1 of 10-bit data 0 bit 0 of 10-bit data 0 8b10bR=1 NOCHALGN[A:B]=1 CV_SELx=1 bit 5 of byte 2 bit 4 of byte 2 bit 3 of byte 2 bit 2 of byte 2 bit 1 of byte 2 bit 0 of byte 2 CV_A1, code violation, byte 1 K_CTRL for byte 1 bit 7 of byte 1 bit 6 of byte 1 bit 5 of byte 1 bit 4 of byte 1 bit 3 of byte 1 bit 2 of byte 1 bit 1 of byte 1 bit 0 of byte 1 CV_A0, code violation, byte 1 K_CTRL for byte 0 bit 7 of byte 0 bit 6 of byte 0 bit 5 of byte 0 bit 4 of byte 0 bit 3 of byte 0 bit 2 of byte 0 bit 1 of byte 0 bit 0 of byte 0
ORCA ORSPI4 Data Sheet
NOCHALGN[A:B]=0 CV_SELx=1 bit 5 of byte 2 bit 4 of byte 2 bit 3 of byte 2 bit 2 of byte 2 bit 1 of byte 2 bit 0 of byte 2 See Table 35 K_CTRL for byte 1 bit 7 of byte 1 bit 6 of byte 1 bit 5 of byte 1 bit 4 of byte 1 bit 3 of byte 1 bit 2 of byte 1 bit 1 of byte 1 bit 0 of byte 1 VL (connected to ground) K_CTRL for byte 0 bit 7 of byte 0 bit 6 of byte 0 bit 5 of byte 0 bit 4 of byte 0 bit 3 of byte 0 bit 2 of byte 0 bit 1 of byte 0 bit 0 of byte 0
Table 35. Definition of the Status Bits of MRWDx that Vary for Different Channels
Channel Index all A A B B C C D Bit Index 39 29 19 29 19 29 19 29 Name CH24_SYNCx CV_A_OR SYNC2_1_OOS CV_B_OR SYNC4_OOS CV_C_OR SYNC2_2_OOS CV_AD_OR Description Multi-channel alignment attempt complete if 1 Code violation in one or more of the received 10-bit groups for channel A Dual channel synchronization of channels A and B not successful if 1 Code violation in one or more of the received 10-bit groups for channel B Quad channel synchronization of SERDES not successful if 1 Code violation in one or more of the received 10-bit groups for channel C Dual channel synchronization of channels C and D not successful if 1 Code violation in one or more of the received 10-bit groups for channel D
The code violation signals will only be valid if the corresponding CV_SELx = "1". (If 8b10bR=0, CV_SEL should also be zero. The CV_x_OR signals are obtained by ORing four code violation signals from the 1:4 DEMUX block. These are primarily indicators of received signal quality, since a single code violation will not force a loss of sync
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ORCA ORSPI4 Data Sheet
(LOS) state in the word alignment state machines. Since these signals come from the DEMUX block, if multi-channel alignment is enabled, the code violation signals correspond to data that must still be multi-channel aligned. Hence these signals provide advance notification of detected violations in data that will appear at the core/FPGA interface several clock cycles later. The exact number of clock cycles that the data is delayed depends on the skew between the incoming data for the different channels. Multi-Channel Alignment Clocking Strategies for the ORSPI4 The data on the four channels SERDES can be independent of each other or can be synchronized in several ways. For example, two channels within the SERDES can be aligned together; channel A and B and/or channel C and D. Alternatively, all four channels in a SERDES quad can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. Clocking strategies for these various modes are described in the following paragraphs. For dual alignment, both twins within a quad can be sourced by clocks that are different from the other channels, however each pair of SERDES must have the same clock. The channel pair A and B is driven on the low-speed side by RSYS_CLK_1 and the channel pair C and D are driven on the low-speed side by RSYS_CLK_2. Either RWCKA or RWCAB can be connected to RSYS_CLK_1, and either RWCKC or RWCKD can be connected to RSYS_CLK_2. A clocking example for dual alignment is shown in Figure 65.
Figure 65. Receive Clocking for a Dual Alignment in a Single Quad
RCK78 TCK78
Common Logic Channel A
2
REFCLK[P:N]
FPGA Logic
RWCKA RSYS_CLK_1 TSYS_CLK_A RWCKB
156.25 MHz
Two Bidirectional Channels of 3.125 Gbits/s Serial Data
Channel B
TSYS_CLK_B RWCKC
Channel C
TSYS_CLK_C RWCKD RSYS_CLK_2 TSYS_CLK_D
Channel D
Two Bidirectional Channels of 3.125 Gbits/s Serial Data
All Clocks at 78.125 MHZ
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ORCA ORSPI4 Data Sheet
For receive quad alignment, RSYS_CLK_1 and RSYS_CLK_2 can be tied together as shown in Figure 66.
Figure 66. Clocking for a Quad Receive Clocking for a Dual Alignment in a Single Quad
RCK78 TCK78
Common Logic Channel A
2
REFCLK[P:N]
FPGA Logic
RWCKA RSYS_CLK_1 TSYS_CLK_A RWCKB
156.25 MHz
Channel B
TSYS_CLK_B RWCKC
Channel C
TSYS_CLK_C RWCKD RSYS_CLK_2 TSYS_CLK_D
Four Bidirectional Channels of 3.125 Gbits/s Serial Data
Channel D
All Clocks at 78.125 MHZ
Multi-channel Alignment Configuration Register settings for multi-channel alignment are shown in Table 36.
Table 36. Multi-Channel Alignment Modes
Register Bits FMPU_SYNCMODE_xx[0:1] 00 10 01 Mode No multi-channel alignment Twin channel alignment Quad channel alignment
To align all 4 channels: * FMPU_SYNMODE_[A:D] = 01 * FMPU_SYNMODE_B[A:D] = 11 To align two channels: * FMPU_SYNMODE_[A:B] = 10 for channel A and B * FMPU_SYNMODE_[C:D] = 10 for channel C and D To enable/disable synchronization signal of individual channel within a multi-channel alignment group: * FMPU_STR_EN_x = "1" enabled * FMPU_STR_EN_x = "0" disabled where x is one of [A:D]. To resynchronize a multi-channel alignment group set the following bit to zero, and then set it to one: * FMPU_RESYNC4 for quad [A:D] * FMPU_RESYNC2_1 for twin channel [A:B]
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* FMPU_RESYNC2_2 for twin channel [C:D]
ORCA ORSPI4 Data Sheet
To resynchronize an independent channel (resetting the write and the read pointer of the FIFO) set the following bit to zero, and then set it to one: * FMPU_RESYNC1_x SERDES Multi-Channel Alignment Sequence 1. Follow steps 1 and 2 in the start up sequence described in a later section. 2. Initiate a SERDES software reset by setting the SWRST bit to "1" and then to "0". Note that, any changes to the SERDES configuration bits should be followed by a software reset. 3. Wait for 3 ms. REFCLK should be toggling by this time. During this time, configure the following registers. Set the following bit in register 30820 - XAUI_MODE_x - set to "1" for XAUI mode or keep the default value of 0 if the Fibre Channel state machine was selected. - Enable channel alignment by setting FMPU_SYNMODE bits in registers 30811 - FMPU_SYNMODE_x. Set to appropriate values for 2, or 4 alignment based on Table 36. - Set RCLKSEL and TCKSEL bits in registers 30821. - RCKSEL - Choose clock source for 78 MHz RCK78 (Table 33). - TCKSEL - Choose clock source for 78 MHz TCK78 (Table 32). Send data on serial links. Monitor the following status/alarm bits: - Monitor the following alarm bits in registers 30000, 30010, 30020, 30030,. - LKI-PLL_x lock indicator. A "1" indicates that PLL has achieved lock. Monitor the following status bits in registers 30804: - XAUISTAT_x - In XAUI mode, they should be 10. - Monitor the following status bits in registers 30805 - DEMUXWAS_x - They should be "1" indicating word alignment is achieved. - CH248_SYNCx - They should be "1" indicating channel alignment. This is cleared by resync. 4. Write a "1" to the appropriate resync register 30820. Note that this assumes that the previous value of the resync bits are "0". The resync operation requires a rising edge. Two writes are required to the resync bits: write a "0" and then write a "1". It is highly recommended to precede a resync with a word alignment, especially in situations where a disturbance in the receive SERDES path can cause misalignment of data and OOS indications without bringing the FC/XAUI state machine to a loss of sync state. A word alignment is achieved by writing a "0" and then a "1" to the appropriate DOWDALIGNx bits in registers 30810.
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ORCA ORSPI4 Data Sheet
Clocking Schemes and Timing Diagrams- SERDES Figure 67 shows a timing diagram for the transmit section of the SERDES interface. Setup and Hold numbers at the interface are also show. Similar timing diagrams are also shown for the receive SERDES interface section in both channel alignment mode (Figure 68), and channel bypass mode (Figure 69).
SERDES Align Mode Interface Figure 67. Data: TBIT9[A:D][3:0], TCOMMA[A:D][3:0], TWD[A:D][31:0] Clock: TSYS_CLK[A:D] 2.5 / 1.3 ns 3.5/0.5 ns Q D Delay D
1.5/0.5 ns
Clock Buffer Delay Relative to Data C Delay
1.1/ 0.18 ns FPGA Clock Tree 3.0ns TCK78 78 MHz /4 SERDES_CLK 311 MHZ Setup = 1.5 ns Hold = - 0.8 ns
FPGA
Embedded Core
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
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SERDES Receive Interface in Channel Alignment Mode
ORCA ORSPI4 Data Sheet
Figure 68. Data: MRWD[A:D][39:0] Clock: RSYS_CLK_1, RSYS_CLK_2
Total prop = 3.6 / 0.75 ns 2.2 / 0.51ns (includes ck to Q) 3.5/0.5 ns D D Delay Clock Buffer Delay Relative to Data C Delay Q
1.5/0.5 ns
1.41/ 0.20 ns FPGA Embedded Core
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
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SERDES Receive Interface in Channel Bypass Mode
ORCA ORSPI4 Data Sheet
Figure 69. Data: MRWD[A:D][39:0] Clock: RWCK[A:D]
Total prop = 3.4 / 0.85 ns 2.5 / 0.7 ns
D Delay
Q
RECOVERED _SERDES_CLK 1.4/ 0.4 ns 311MHz
Delay C RWCK[A:D]
/4
RCK78[A:D]
Delay
FPGA
Embedded Core
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER Test Modes In addition to the operational logic described in the preceding sections, the SERDES contains logic to support various test modes - both for device validation and evaluation and for operating system level tests. The following sections discuss two of the test support logic blocks, supporting various loopback modes, in addition to SERDES characterization pins. Loopback Testing Loopback testing is performed by looping back (either internal to the SERDES, by configuring the FPGA logic or by external connections) transmitted data to the corresponding receiver inputs, or received data to the transmitter output. The loopback path may be either serial or parallel. In general, loopback tests can be classified as "near end" or "far end". In "near end" loopback (Figure 70(a)), data is generated and checked locally, i.e. by logic on, or connection of, test equipment to the same card as the FPSC. In "far end" loopback (Figure 70(b)), the generating and checking functions are performed remotely, either by test equipment or a remote system card.
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Figure 70. "Near End" vs. "Far End" Loopback. (NOTE: xx = A, B, C, or D)
Device Under Test (DUT) Data Checking Test Equipment or Logic on Local System Card Data Generation (a) "Near End" Loopback
n TWDxx[31:0] TCOMMAxx[3:0] TBIT9xx[3:0] FPGA Logic m MRWDxx[39:0] 40
Receive
ORCA ORSPI4 Data Sheet
Embedded Core
CML Buffer CML Buffer
HDIN[P:N]_xx 2
Non-Functional
32 4 4
Transmit
HDOUT[P:N]_xx 2
Active (to Eye Diagram Measurement or remote System Card)
High Speed Serial Loopback Connection
Device Under Test (DUT)
FPGA Logic m
Active (to Logic on Local System Card)
Embedded Core 40
SERDES Block
HDIN[P:N]_xx 2
MRWDxx[39:0]
DE MUX
8B/10B SERDES CML Buffer
Data Generation Test Equipment or Logic Remote System Card
Receive
HDOUT[P:N]_xx
n
Non-Functional
TWDxx[31:0] TCOMMAxx[3:0] TBIT9xx[3:0]
32 4 4
Transmit
8B/10B
SERDES
CML Buffer
2
Data Checking
(b) "Far End" Loopback
Parallel Loopback Connection
The loopback mode can also be characterized by the physical location of the loopback connection. There are two possible loopback modes supported by the SERDES logic: * High-speed serial loopback at the CML buffer interface (near end) * Parallel loopback at the SERDES boundary (far end) These two loopback modes are described in more detail in the following sections. As noted earlier, other specialized loopback modes can be obtained by configuration of the FPGA logic or by connections external to the FPSC. High-Speed Serial Loopback at the CML Buffer Interface The high-speed serial loopback mode has the serial transmit signals looped back internally to the serial receive circuitry. The internal loopback path is from the input connection to the transmit CML buffer to the output connection from the receive CML buffer. The data are sourced on the TWDx[31:0], TCOMMAx[3:0] and TBIT9x[3:0] signal lines and received on the MRWDx[39:0] signal lines. The serial loopback path does not include the high-speed input and output buffers. If TESTEN_x is set, the HDOUTP_x and HDOUTN_x outputs are active in this mode while the CML input buffers are powered down. The device is otherwise in its normal mode of operation. This mode is normally used for tests where the data source and destination are on the same card and is the basic loopback path shown in Table 37. The data rate selection bits, TXHR and RXHR, in the channel configuration registers must be configured to carry the same value. Table 37 summarize the settings of the control interface register configuration bits for high-speed serial loopback.
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ORCA ORSPI4 Data Sheet
Table 37. High-Speed Serial Loopback Configuration Bit Definitions for the SERDES
Register Address 30002, 30012, 30022, 30032 Bit Value Bit 0 = 0 or 1 Bit 7 = 0 or 1 Bit Name TXHR 8B10BT Comments Set to "0" or "1". TXHR and RXHR bits must be set to the same value. Set to "0" or "1". If set to "0", the 8b/10b encoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to the same value.
30801
Bit 0 = 1 (Channel A) Bit 1 = 1 (Channel B) Bit 2 = 1 (Channel C) Bit 3 = 1 (Channel D)
LOOPENB_xx Set any of the bits 0-3 to "1" to do serial loopback on the corresponding channel.* The high-speed serial outputs will not be active.
*This test mode can also be set using TESTEN_xx in place of LOOPENB_xx. In that case, Test Mode must be set to 00000.
Parallel Loopback at the SERDES Boundary In this parallel loopback, differential data are received at the HDINP_x and HDINN_x pins and are retransmitted at the HDOUTP_x and HDOUTN_x pins. The loopback path is at the interface between the SERDES blocks and the MUX and DEMUX blocks and uses the parallel 10-bit buses at these interfaces (see Figure 70b). The loopback connection is made such that the input signals to the TX SERDES block is the same as the output signals from the RX SERDES block. In this parallel loopback mode, the MRWDx[39:0] signal lines remain active and the TWDx[31:0], TCOMMAx[3:0] and TBIT9x[3:0] signal lines are not used. This mode is normally used for tests where serial test data is received from and transmitted to either test equipment or via a serial backplane to a remote card and is the basic loopback path shown earlier in Figure 70(b). The data rate selection bits TXHR and RXHR in the channel configuration registers must be configured to carry the same value. Also, the 8b/10b encoder and decoder are excluded from the loopback path by setting the 8b10bT and 8b10bR configuration bits to "0". Table 38 illustrates the control interface register configuration for the parallel loopback.
Table 38. Parallel Loopback at the SERDES Boundary Configuration Bit Definitions for the SERDES
Register Address (Hex) 30002, 30012, 30022, 30032 Bit Value Bit 0 = 0 or 1 Bit 7 = 0 Bit Name TXHR 8b10bT Comments Set to "0" or "1". TXHR and RXHR bits must be set to the same value. Set to "0" The 8b/10b encoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to "0". Set to "0" or "1". TXHR and RXHR bits must be set to the same value. Set to "0". The 8b/10b decoder is excluded from the loopback path. The 8b/10b encoder and decoder selection control bits must both be set to "0". SET to "1" if the loopback is done globally on all four channels. Set to 00001
30003, 30013, 30023, 30033
Bit 0 = 0 or 1 Bit 3 = 0
RXHR 8b10bR
30005 30006, 30016, 30026, 30036
Bit 7 = 1 Bits[4:0]
GTESTEN Testmode
SERDES Characterization Test Mode The SERDES characterization mode is a test mode that allows for direct control and observation of the transmit and receive SERDES interfaces at chip ports. With these modes the SERDES logic and I/O can be tested one channel at a time in either the receive or transmit modes. The SERDES test mode requires that the SERDES block be selected instead of the SPIB block during the Module Generation phase of the ORSPI4 in ispLEVER. In addition, the TESTMD[1:0]N signals need to be set to "0" during SERDES characterization.
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ORCA ORSPI4 Data Sheet
The SERDES characterization test mode is configured by setting bits in the control registers via the system bus. The transmit characterization test mode is entered when SCHAR_ENA= "1" (address 30830, bit 4) and SCHAR_TXSEL= "1" (address 30830, bit 5). Entering this mode will cause chip port inputs to directly control the SERDES low-speed transmit ports of one of the channels as shown in Table 39.
Table 39. SERDES Transmit Characterization Mode
Required Inputs TESTMD[1:0]N=00, SCHAR_EN=1, SCHAR_TXSEL=1 Inputs Used During Mode TBCx (transmit) PMIA15 LDIN9x PMIA14 LDIN8x PMIA13 LDIN7x PMIA11 LDIN6x PMIA9 LDIN5x PMAI8 LDIN4x PMIA7 LDIN3x PMIA6 LDIN2x PMIA5 LDIN1x PMIA4 LDIN0x PMIA2
The x in the table represents a single channel in the SERDES QUAD, selected by the SCHAR_CHAN control bits (address 30830, bits 6 and 7). The decoding of SCHAR_CHAN is shown in Table 40.
Table 40. Decoding of SCHAR_CHAN
SCHAR_CHAN0 0 1 0 1 SCHAR_CHAN1 0 0 1 1 Channel A B C D
The receive characterization test mode is entered as long as TESTMD[1:0]N = 00. In this mode, one of the channels of SERDES outputs is observed at chip ports as shown in Table 41. The channel that is observed is also based on the decoding of SCHAR_CHAN as shown in Table 40. The receive characterization pins can be observed independently, whether the transmit characterization pins are enabled or not.
Table 41. SERDES Receive Characterization Mode
Required Inputs TESTMD[1:0]N=00 Outputs Used During Mode TBC311 PMID20 CV PMID21 BYTSYNC PMID22 WDSYNC PMID23 RBCO PMID24 RBC1 PMID25 LDOUT9 PMID26 LDOUT8 PMID 27 LDOUT7 PMID28 LDOUT6 PMID29 LDOUT5 PMID30 LDOUT4 PMID31 LDOUT3 PMID32 LDOUT2 PMID33 LDOUT1 PMID34 LDOUT0 PMID35
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ORCA ORSPI4 Data Sheet
Memory Controller Functional Description
The ORSPI4 device includes a Memory Controller interface to an external second generation Quad Data Rate (QDRII) memory. This is provided for additional data buffering beyond the embedded DPRAMs. In this case, the embedded DPRAMs are used as clock-crossing domain FIFOs. The key requirement for this memory interface is the support of a throughput of greater than 20 Gbits/s so that all the data received on the SPI4 interface at 10 Gbits/s can be buffered. A QDRII SRAM supports this throughput with 32 unidirectional data lines. A 36-bit interface is provided to allow for parity or control bits to be added. The controller block provides the ability to access an external QDRII SRAM through the FPGA. A set of 72 input data and 72 output data signals are available across the core-FPGA interface. Of the 72 signals, eight can be used either for parity or for data. The core passes the data transparently to and from the QDRII SRAM in two-word or four-word bursts. The data interfaces to memory are 36 bits wide and the address bus is 18 bits wide. This supports the interfaces required for a 512K x 36 bit (18 Mbit) QDRII SRAM. The basic blocks of the Memory Controller are: * FIFOs for Write Data and Instructions * FIFOs for Read Data and Instructions * Read and Write Controllers (including FIFO and memory interface state machines) * Address Multiplexer (MUX) * Write Data DEMUX and Read Data Capture/MUX Blocks A logical block diagram of the Memory Controller is shown in Figure 71. Details of the individual blocks are outlined in the following sections. The blocks are described in sequence for a write from the FPGA and a subsequent read to the FPGA.
Figure 71. ORSPI4 QDRII Memory Controller Block Diagram.
ORSPI4 Device
FPGA Logic
External Memory
QDRII SDRAM
ORSPI4 QDR II Core
MCREFCLK ATREFCLK BTREFCLK
F_MC_REFCLK MC_SYSCLK F_MC_WD MC_WDFIFO_FULL F_MC_WDFIFO_WE 74 Full WE
Clock Select #1
74
PLL
COUT = CIN * N/M COUT = CIN / 2
Clock Select #2
PMIK
K
72 2
Write Data FIFO
RST
Empty RE
Enable Write Enable Enable 18
RST
Write Data Demux
RST
PMID
36
D
F_MC_WCLK 32
Write Clock Empty RE 32
F_MC_WI MC_WIFIFO_FULL F_MC_WIFIFO_WE
Full WE
Write Instruction FIFO
RST
Write Controller
PMIWN
W#
Address Mux
18
PMIA
18
SA
F_MC_RI MC_RIFIFO_FULL F_MC_RIFIFO_WE
32 Full WE
Read Instruction FIFO
RST
32 Empty RE
F_MC_RCLK
Read Clock Full WE
Read Controller
RST
RST
Read Enable
PMIRN
R#
MC_RD MC_RDFIFO_EMPTY F_MC_RDFIFO_RE FPGA_RESET_MC
72 Empty RE
Read Data FIFO
RST
72
Read Data Mux/ Capture
RST
PMIQ PMIC
36
Q CQ
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Lattice Semiconductor FPGA/Memory Controller Core Interface Description
ORCA ORSPI4 Data Sheet
Table 42 lists the signals at the FPGA/Core interface for the Memory Controller block.
Table 42. FPGA/Embedded Core Signals
Signal F_MC_WD[73:0] F_MC_WI[31:0] MC_RD[71:0] F_MC_RI[31:0] MC_WDFIFO_FULL MC_WIFIFO_FULL MC_RDFIFO_EMPTY MC_RIFIFO_FULL F_FMC_WDFIFO_WE F_FMC_WIFIFO_WE F_FMC_RDFIFO_RE F_FMC_RIFIFO_WE F_MC_WCLK F_MC_RCLK MC_SYSCLK F_MC_REFCLK FPGA_RESET_MC Direction From /To Description
QDRII SRAM Read/Write Control FPGA Core Write data to Memory Controller Write Data FIFO FPGA Core Write instruction to Memory Controller Read Instruction FIFO Core FPGA Read data from Memory Controller Read Data FIFO FPGA Core Read instruction to Memory Controller Write Instruction FIFO Core FPGA Core FPGA Core FPGA Core FPGA Full flag from MC Write data FIFO. Full threshold is set by the MC_FULL_THRESHOLD register bits. Full flag from MC Write instruction FIFO. MC_WIFIFO_FULL high indicates that only one more instruction can be written to the instruction FIFO. Empty flag from MC Read data FIFO. Empty threshold is set by the MC_EMPTY_THRESHOLD register bits. Full flag from MC Read instruction FIFO. MC_RDFIFO_FULL HIGH indicates that only one more instruction can be written to the instruction FIFO.
FPGA Core Write enable to Write Data FIFO FPGA Core Write enable to Write Instruction FIFO FPGA Core Read enable to Read data FIFO FPGA Core Write enable to Read Instruction FIFO FPGA Core Memory Controller Write clock FPGA Core Memory Controller Read clock Core FPGA Internal system clock for the Memory Controller i/f FPGA Core Memory Controller Reference clock FPGA Core Memory Controller Asynchronous Soft Reset
Memory Controller - Detailed Description
Write Data and Instruction FIFOs The Write Data FIFO (WDFIFO) stores data written into it by logic in the FPGA. The configuration is 64 by 74 bits. Read/write pointers and fill-level logic is included. The FIFOs also function as an asynchronous clock domain boundary between the FPGA generated write clock and the Memory Controller (MC) system clock (MC_SYSCLK). Writes from the FPGA that are asynchronous to the memory clock (K, K#) are allowed. It is also possible to run the FIFO in synchronous mode by looping back the 1x clock via the FPGA to the FIFO write clock (MC_WCLK). A set of 72 data signals is available across the core-FPGA interface. Of the 72, eight signals can be either used for parity or data. The core, however, passes the data transparently to the QDRII SRAM. Data length is specified in terms of FIFO lines. If data length is > 64 FIFO lines, then the user must segment the data. The Write Instruction FIFO (WIFIFO) is configured 4 by 32 bits respectively, in order to store up to 4 instructions that are written to the MC by logic in the FPGA. The instruction fields are ID (data/address coherency), data length (number of cache lines) and address (for QDR memory). Write instruction and data word formats are shown in Figure 72.
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Figure 72. Write Data and Instruction Word Formats
Write Instruction Word
31 30 29 28 27 24 23 Data length 18 17
ORCA ORSPI4 Data Sheet
0
Reserved
ID bits
Reserved
Address
Write Data Word
73 ID bits 72 71 Write Data 0
The user starts a write cycle by writing data to the WDFIFO. The maximum data length is 63 lines deep and the minimum is one 72-bit data word (or one line). The user provides the instruction word associated with a data string during the write period for the last word of the data. This sequence can continue to repeat as long as the MC_WxFIFO_FULL flags from the embedded core remain inactive. Once the MC_WIFIFO_FULL flag is asserted, the user may send data words to the WDFIFO locations (assuming the MC_WDFIFO_FULL flag has not been asserted) and write one last instruction word to the instruction FIFO as the last data word is written into the data FIFO. The timing diagram for the write interface for a typical write sequence is shown in Figure 73. The write sequence in this case consists of writing 32 words to location A0 followed by one word each to locations A1, A2, A3 and A4. The MC_WIFIFO_FULL is asserted after the instruction for location A2 has been written, indicating that only one more instruction may be written to the instruction FIFO. The write to location A4 cannot occur until the MC_WIFIFO_FULL flag is deasserted. The MC_WDFIFO_FULL flag remains low in this case since the full threshold for the data FIFO has not been reached
Figure 73. ORSPI4 Memory Controller Interface to FPGA -- Write Timing Diagram
F_MC_WCLK
F_MC_WDFIFO_WE
F_MC_WD(73:72)
00
01
10
11
00
F_MC_WD(71:0)
D0-0
...
D0-31
D1-0
D2-0
D3-0
D4-0
F_MC_WIFIFO_WE
F_MC_WI(25:24)
00
01
10
11
00
F_MC_WI(23:18)
D*32
D*1
D*1
D*1
D*1
F_MC_WI(17:0)
A0
A1
A2
A3
A4
MC_WIFIFO_FULL
In the first clock cycle, the first word of the data burst is written along with the ID bit value of 00. The instruction word is updated on the last word of a data burst and contains the ID bit value, address and length of the data burst. The maximum burst length is set by the depth of the data FIFO, which is 64 FIFO lines. The data length in the
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ORCA ORSPI4 Data Sheet
instruction word is provided in terms of FIFO lines. Data length for data associated with A0 is shown to be 32 lines. The maximum burst length is set by the depth of the data FIFO which is 64 FIFO lines. Data is presented as 9 bytes in every MC_WCLK cycle. A new data word always begins at bit position 71 and has a unique 2-bit ID. The transition from one ID value to another indicates the start of a new data burst as shown in Figure 72. For each burst, the values of the ID fields in the data word and the instruction word are compared. The write controller first waits for the empty flag from the instruction FIFO to be deasserted and processes the first pending instruction. The core reads the instruction word first. Based on the data length, the core starts to read the appropriate amount of data from the data FIFO. The address and data length are passed to the write controller state machine. After the last data word has been read from the data FIFO, the core increments the instruction FIFO address to the next pending instruction. The 2-bit ID field in each data word is compared to the 2-bit ID field in the processed instruction to maintain data/instruction coherency. If the ID fields in the data and instruction words do not match, an error is sent to a software register bit. It is the responsibility of the FPGA to provide the exact amount of data specified in the data length field of the instruction word. A programmable FIFO full flag (MC_WDFIFO_FULL) is available to the FPGA for the data FIFO. The FIFO flag threshold is set by the 4-bit software register field MC_FULL_THRESHOLD. If the MC_WDFIFO_FULL flag is programmed to indicate a truly full condition, the FPGA logic must assure that the FIFO does not overrun and that an instruction word is written in parallel with the final data word of a sequence. Address Multiplexer (MUX) Address information to the QDRII SRAM is multiplexed between the write port and the read port. This is possible since data is always transferred in two-word or four-word bursts (word is 36-bits). Logic in the SRAM supplies the address least significant bits for the two-word burst case and the lower two LSbs in the case of four-word bursts. It is however, necessary to make sure read and write addresses do not contend for the address bus. This function is performed by the Address MUX logic based on signals from the Memory Read Controller (MRC) and Memory Write Controller (MWC). Figure 74 and Figure 75 show the timing of signals at the QDRII SRAM interface for two-word and four-word reads and writes. The burst size is selectable through the field MC_BURST_MODE in the configuration registers 30B03[0]. Write data is sent on the first rising edge of the positive clock signal (K), after the write address is provided. Read data is returned on the second rising edge of K, after the read address is provided. If a sequence of read and write addresses is sent, both read data and write data are available simultaneously. It is this feature that gives the QDRII SRAM its high throughput. Note: Except for one address signal, there is no requirement that PMIA address signals be connected to a particular address input on the QDRII SRAM, since writes and reads share the one and only address bus. The only exception is PMIA17, which is only used in 2-word mode, and thus must be connected to the corresponding QDRII SRAM address input that is only present on the 2-word device (if 2-word/4-word compatibility is to be maintained). Flexibility in assigning these signals can be useful in optimizing the layout of this bus.
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ORCA ORSPI4 Data Sheet
Figure 74. .ORSPI4 Memory Controller Interface to QDRII: 4-Word Burst Mode
K
K#
R#
R1
R2
W#
W1
W2
SA
R1
W1
R2
W2
D
W1a
W1b
W1c
W1d
W2a
W2b
W2c
W2d
Q
R1a
R1b
R1c
R1d
R2a
R2b
R2c
R2d
Figure 75 shows the timing of signals at the QDRII SRAM interface for two-word reads and writes. In this case, address data is sent on both the rising and falling edges of the positive clock signal. Write data is sent on the first rising edge of K before the write address and second data word are provided on the falling edge. As in the fourword case, read data is returned on the second rising edge of K after the read address is provided (on a rising edge of the positive clock).
Figure 75. ORSPI4 Memory Controller Interface to QDRII: 2-Word Burst Mode
K
K#
R#
R1
R2
R3
R4
W#
W1
W2
W3
W4
SA
R1
W1
R2
W2
R3
W3
R4
W4
D
W1a
W1b
W2a
W2b
W3a
W3b
W4a
W4b
Q
R1a
R1b
R2a
R2b
R3a
R3b
R4a
R4b
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ORCA ORSPI4 Data Sheet
Write Controller and Write Data DEMUX The write timing shown in Figure 74 and Figure 75 is generated by the Memory Write Controller (MWC) logic based on instruction and status signals from the write FIFOs and synchronization information from the Memory Read Controller (MRC). The MWC has two functions. First it will read the instruction words from the instruction FIFO and separate the bit fields into address, ID and Data length. Then it will generate write cycle timing based on the type of memory configured (2 or 4 word burst). The MWC will also do data/instruction data coherency (ID) checking and generate an error (output MC_ID_STATUS) if the test fails. The write controllers run at 2x the clock rate (MCLCKx2) in order to generate the QDRII SRAM data and address timing correctly in relation to the differential memory clock (K, K#). The MWC must also arbitrate with the MRC to ensure that there is no contention between SRAM read and write cycles, as discussed in the previous section. The MWC generates enables to initiate burst writes. Separate read and write address counters are required and are loaded by the controllers with the content of the address field in the instruction word. In order to support 512k x 36 RAM in 2-word burst mode, 18 active address lines are required, whereas in 4-word burst mode, 17 are required. Data to the QDRII SRAM must also be demultiplexed (DEMUX) by the Write Data DEMUX block in order to convert from the MC internal format of 72 bit buses to the 36-bit DDR format for the QDR SRAM. Read Data Capture, MUX and Read Controller The read timing shown in Figure 74 and Figure 75 is generated by the Memory Read Controller (MRC) logic, based on information from the read instruction FIFO. The MRC has two functions. First it will read the instruction words from the instruction FIFO and separate the bit fields into address and data length information. Then it will generate read cycle timing, based on the type of memory configured (2 or 4 word burst) and provide synchronization information to the Memory Write Controller (MWC). The read controller generates enables to initiate the read cycle. A separate read address counters is required and is loaded by the controller with the content of the address field in the instruction word. As was true with the MWR, to support 512k x 36 RAM in two word burst mode, 17 active address lines are required, whereas in 4-word burst mode, 18 are required. Data from the QDR RAM must also be multiplexed (MUX) in order to convert to the MC internal format of 72 bit buses from the 36-bit DDR format for the QDRII SRAM. In order to capture the SRAM read data the echo clocks (CQ, CQ#) generated by the SRAM are used to latch the data. This is the most robust and flexible of schemes available to capture the data, as with this source synchronous technique, the impact of round trip delays from the data leaving the Memory Controller, to data being received back can be minimized. The outputs of the capture latches are retimed back into the MCLK2x domain in order to be written to the Read Data FIFO (RDFIFO) discussed in the next section. Read Data and Instruction FIFOs The Read Data FIFO (RDFIFO) is used to store the data that is returned from the QDRII SRAM. It is asynchronously read by logic in the FPGA. The RDFIFO size is 64 X 72 bits. The Read Instruction FIFO (RIFIFO) is similar to the WIFIFO and is configured 4 by 32 bits respectively in order to store up to 4 instructions that are written to the MC by logic in the FPGA. The instruction fields are data length (number of cache lines to read) and address (for QDR memory). The read instruction and data word formats are shown in Figure 76 and Figure 77 respectively.
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Figure 76. Read Data and Instruction Word Formats
Read Instruction Word
31 Reserved (low) 24 23 18 Data Length 17
ORCA ORSPI4 Data Sheet
0 Address
71
Read Data Word
Read Data
0
Figure 77. ORSPI4 Memory Controller Interface to FPGA -- Read Timing Diagram
F_MC_RCLK
F_MC_RIFIFO_WE
F_MC_RI(23:18)
D0*2
D1*1
D2*1
D3*8
D1-0
D4*1
F_MC_RI(17:0)
A0
A1
A2
A3
D1-0
A4
MC_RIFIFO_FULL
MC_RDFIFO_EMPTY
F_MC_RDFIFO_RE
MC_RD(71:0)
D0-0
D0-1
D1-0
D2-0
The user can write/read instructions into the read instruction FIFO as long as the MC_RIFIFO_FULL flag is low. If this flag is high, the FIFO can accept one more instruction. The user can start reading data from the read data FIFO once the MC_RFIFO_EMPTY flag goes low. It is the responsibility of the user to: * Maintain count of data from the read data FIFO and check if they match the data length provided in the corresponding instruction word * Associate the data received with the address. Data will be received in the same order as they were requested. The timing diagram for the read interface for a typical read sequence is shown in Figure 77. The read sequence in this case consists of reading 2 words from location A0 followed by one word each from locations A1, A2, eight words from A3 and one word from A4 and A5. The MC_RIFIFO_FULL is asserted after the instruction for location A2 has been written, indicating that only one more instruction may be written to the instruction FIFO. The read instruction write to access location A4 cannot occur until the MC_RIFIFO_FULL flag is deasserted. The MC_RDFIFO_EMPTY flag remains high until data has been read from the QDRII SRAM and is available to the FPGA logic.
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ORCA ORSPI4 Data Sheet
A programmable FIFO empty flag (MC_RDFIFO_EMPTY) is available to the FPGA for the data FIFO. The FIFO flag threshold is set by the 4-bit software register field MC_EMPTY_THRESHOLD. Memory Controller Instruction Latency An example of the instruction latency through the QDR II Memory Controller for write instructions is shown in Figure 78. For this example, it is assumed that the clock from the FPGA logic to the Memory Controller (F_MC_WCLK) is synchronized to the K clock to the external memory. If these clocks are not synchronous, then the latency may vary.
Figure 78. ORSPI4 QDR II Memory Controller - FPGA to External Memory Latency Example
F_MC_WCLK = External Memory K Clock
F_MC_WDFIFO_WE
Internal FPGA Logic to Memory Controller Interface
F_MC_WD(73:72)
00 D0-0 ... D0-31
F_MC_WD(71:0)
F_MC_WIFIFO_WE
F_MC_WI(25:24)
00 D*32 A0
F_MC_WI(23:18)
F_MC_WI(17:0)
ORSPI4 to External Memory Interface
External Memory K Clock
External Memory W#
W1
2 K clock cycles instruction latency
The latency for read instructions is the same given the same clock relationship conditions. Memory Controller Status Reporting The following status or alarms will be reported to the user through software register bits: * Data length mismatch from the write controller state machine. This alarm bit will be set if a block of data read from the write data FIFO does not match the data length from its associated instruction. * Data-instruction coherency error. This alarm bit will be set if the ID field in write data and its associated write instruction do not match. * Write data, Read data FIFO overrun and underrun errors. Clocking Schemes and Timing Diagrams- Memory Controller The Memory Controller Unit requires three clocks: * MC_WCLK from the FPGA, which controls the FPGA-side accesses to the Write Instruction and Write Data 142
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FIFOs (Figure 71).
ORCA ORSPI4 Data Sheet
* MC_RCLK from the FPGA, which controls the FPGA-side accesses to the Read Instruction and Read Data FIFOs. * The main clock for the unit is selected by MC_ICK_SEL (configuration register 30B03[2:3]) which controls all remaining clocking, including the clocks supplied to the external QDR-II SRAM. This clock can be sourced as follows: - - - - MC_ICK_SEL = 0 selects the dedicated Memory Controller external clock input MCREFCLK = Freq_In MC_ICK_SEL = 1 selects the SPIA unit's external clock ATREFCLK = Freq_In; MC_ICK_SEL = 2 selects the SPIB unit's external clock BTREFCLK = Freq_In, or MC_ICK_SEL = 3 selects the FPGA-supplied signal F_MC_REFCLK= Freq_In.
The above-selected clock, can then be modified in frequency, by MC_OCK_SEL (configuration register 30B03[7]) as follows: - MC_OCK_SEL = 0 selects a PLL, such that Freq_Out = (Freq_In * (PLL_N + 1)/(2 * (PLL_M + 1))); or - MC_OCK_SEL = 1 selects a divide-by-2, such that Freq_Out = (Freq_In / 2). The PLL_N value is obtained from the configuration register 30B04[1:3]. PLL_M value is obtained from configuration register 30B04[5:7]. At the right side of the four internal FIFOs in Figure 71, the data is transferred as two 36-bit words per Freq_Out clock cycle, but is then time-multiplexed into a single 36-bit DDR bus operating at frequency (Freq_Out * 2) for transfer to the external QDR-II SRAM. The clock supplied to the QDR-II SRAM is at frequency Freq_Out. Figure 79 through Figure 85 show the timing diagrams for the embedded controller/FPGA interface.
Figure 79. Data: F_MC_WD[73:0], F_MC_WI[31:0], F_MC_RI[31:0] Clock: F_MC_WCLK
2.4/ 0.75 ns 3.5/0.5 ns Q D Delay FIFO Clock Buffer Delay Relative to Data C Delay
1.5/0.5 ns
1.1/ 0.74 ns FPGA Embedded Core Setup= 1.6 ns Hold = 0.3 ns
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
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Figure 80. F_MC_RI[31:0] Clock: F_MC_RCLK
ORCA ORSPI4 Data Sheet
2.4/ 0.75 ns 3.5/0.5 ns Q D Delay FIFO Clock Buffer Delay Relative to Data C Delay
1.5/0.5 ns
1.35/ 0.85 ns FPGA Embedded Core Setup = 1.4 ns Hold = 0.4 ns
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
Figure 81. F_MC_WIFIFO_WE, F_MC_WDFIFO_WE Clock: F_MC_WCLK
2.7/ 0.73 ns 3.5/0.5 ns D Q Delay FIFO Clock Buffer Delay Relative to Data C Delay
1.5/0.5 ns
1.7/ 0.75 ns FPGA Embedded Core Setup= 2.8 ns Hold = 0.37 ns
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
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Figure 82. F_MC_RDFIFO_RE, F_MC_RIFIFO_WE Clock: F_MC_RCLK
2.5/ 0.76 ns 3.5/0.5 ns D Q Delay
ORCA ORSPI4 Data Sheet
D
Q
1.5/0.5 ns
Clock Buffer Delay Relative to Data C Delay
1.92/ 0.85 ns FPGA Embedded Core Setup= 2.0 ns Hold = 0.45 ns
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
Figure 83. Data: F_MC_RD[71:0] Clock: F_MC_RCLK
Total prop = 3.6 / 1.3 ns 1.36 / 0.38 ns 3.5/0.5 ns D D Q Delay
1.5/0.5 ns
Clock Buffer Delay Relative to Data C
Delay
1.94/ 0.83 ns FPGA Embedded Core
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
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Figure 84. Data: F_MC_WIFIFO_FULL, MC_WDFIFO_FULL Clock: F_MC_WCLK
ORCA ORSPI4 Data Sheet
Total prop = 2.7 / 1.12 ns 1.36 / 0.38 ns 3.5/0.5 ns D D Q Delay
1.5/0.5 ns
Clock Buffer Delay Relative to Data C Delay
1.7/ 0.73 ns FPGA Embedded Core
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
Figure 85. Data: F_MC_RIFIFO_FULL, MC_RDFIFO_EMPTY Clock: F_MC_RCLK
Total prop = 3.0 / 1.3 ns 0.92 / 0.32 ns 3.5/0.5 ns D D Delay Q
1.5/0.5 ns
Clock Buffer Delay Relative to Data C Delay
1.93/ 0.84 ns FPGA Embedded Core
NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER
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ORCA ORSPI4 Data Sheet
Software
Software for Configuration
There are two ways to write to the ORSPI4 memory map either via MPI (Microprocessor Interface) or via UMI (User Master Interface) to the FPGA logic. Both the interfaces use the system bus to perform the transactions with the registers. The MPI is provided to talk to any Power PC microprocessor whereas UMI is used for any customerdefined interface and interfaces extremely well with ORCASTRATM to graphically change and monitor the register map. The registers are divided into different domains, the details of which can be found in the technical note TN1017. ORSPI4 device core registers can be accessed by addressing the 30000 onwards domain. Since there are four different macros inside the ORSPI4 core, all these macros have been assigned their individual sub domains.
Table 43. Address Allocation - Register Elements
Address (0x) Description
309xx 30Axx 308xx 30Bxx
SPIA addresses SPIB addresses SERDES addresses QDR MEM controller addresses and some shared by SPIA and SPIB
ORSPI4 Start-up Sequence
SPI4 Link Start-up Protocol Immediately after reset, and before the link synchronization, the SPI4 link must initialize to a known interface protocol. This section describes the initialization protocol for a generic SPI4 link. The actual start-up procedure with the appropriate software register settings is described in the next section. Figure 86 shows the SPI4 link reference diagram that is referenced in the descriptions below. Where appropriate, the corresponding ORSPI4 software register settings are also described as relevant to this start-up protocol. A reset can be either hard or soft, but is assumed that the entire SPI4 link is being reset. Immediately after the reset signal is deasserted and before the link synchronization, the following actions/conditions must occur/exist.
Figure 86. SPI4 Link Functional Block Diagram
Device A Device B
TX_D_A
RX_D_B
DIP2 = "OK" TX_S_A
DIP4 = "OK"
RX_S_B
1. The Receive Data FIFOs are emptied (RX_D_B)
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2. Any outstanding credits are cleared in the Transmit Data Path (TX_D_A)
ORCA ORSPI4 Data Sheet
- This is done by presetting all the Credit values in the TX credit memory to 10'h000. This is done by first selecting the TX credit memory by writing a `1' to TX_CRED_MEM_SEL (Address 30917 in SPIA and 30A17 in SPIB) and then writing to address range 31000-310FF that correspond to locations 0 - 255 in the TX credit memory. - Additionally, the STAT fields for all ports must be disabled to 2'b11. This can be done by first selecting the TX status memory by writing a `1' to TX_STAT_MEM_SEL (Address 30917 in SPIA and 30A17 in SPIB) and then writing to address range 31000 - 310FF that correspond to locations 0 - 255 in the TX status memory. 3. The Data Transmitter (TX_D_A as shown in Figure 86) sends continuous Training Patterns until it receives valid FIFO status on TX_S_A. A signal from the status block needs to be sent to the data block to indicate this. The Transmit PDM polling is disabled at this point. 4. The Receive Data interface RX_D_B ignores all incoming data until it has observed the training pattern and acquired synchronization. This can be observed by polling the RX_DSKW_DONE_STS and RX_DSKW_ERR_STS interruptible status bits (Address 3091C in SPIA and 30A1C in SPIB). This is described in detail in the next section. As long as the receiver is not deskewed (or synchronization is not complete), RX_S_B will continue to send framing pattern 2'b11 on the SPI4 status link. 5. RX_D_B asserts DIP-4 = "OK" which is indicated by a `0' on the RX_ALGN_OFF_STS interruptible status bit (Address 3091C in SPIA and 30A1C in SPIB). This bit is set to `1' if the number of consecutive DIP-4 errors exceeds the programmed threshold. This threshold is programmed by writing to RX_DIP4_ERR_TH control register bits (Address 30910 in SPIA and 30A10 in SPIB). 6. After the receiver has declared link synchronization and a calendar has been provisioned, the Receive Status Channel RX_S_B begins sending valid FIFO status for each enabled port contained in the Calendar. Valid Status is Frame-based with DIP-2 code words as part of the protocol. Calendar is declared as "provisioned" when RX_CAL_LEN_MAIN (or RX_CAL_LEN_SHD if shadow calendar is being used) has a value > 0. It is recommended to configure the calendar table and write the RX_CAL_LEN_MAIN last. 7. After the Transmitter Status Channel TX_S_A receives a configurable number of consecutive valid DIP-2 code words, it begins transmitting data bursts of the enabled ports within the configured Calendar. The DIP-2 error threshold can be programmed by writing to TX_DIP2_ERR_TH (Address 30944 in SPIA and 30A44 in SPIB). At this point the end-to-end link is established and valid data/status is being transferred across the SPI4 link. There may be cases where the Transmitter in Device "A" (TX_D_A) is active, but the Receiver in Device "B" (RX_D_B) is in reset condition. In this situation, after the Receive Reset signal has been deasserted, the link follows the procedure defined above from Step 4. When the receiver is in a reset condition, the RX_S_B block will be sending the "1 1" framing pattern to the Transmit Status Channel interface (TX_S_A). The transmitter will follow the procedure prescribed above as well. There are also cases where the Data Path transmitter in Device "A" (TX_D_A) is in a reset condition, and the Receiver in Device "B" (RX_D_B) is active. In this situation, after the Transmit Reset signal is deasserted, the link follows the procedure defined above from Step 2. When the transmitter is in a reset condition, the RX_D_B block will not be receiving valid DIP-4 values. The RX_D_B block removes the DIP-4 = "OK" signal and the RX_S_B block begins to send continuous "1 1" framing pattern to the Transmit Status Channel interface (TX_S_A). SPIA or SPIB Start-up sequence After the device is powered up, it resets itself with a Power-up reset, designed to trigger itself at power up. The first thing required by the ORSPI4, is to perform baseline process followed by training if dynamic alignment is chosen (SPI4_LOW_SPEED_DATA_SEL = `0'). This is required by the SPIA and SPIB high-speed receivers for internal
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ORCA ORSPI4 Data Sheet
alignment. Dynamic alignment may also be required during normal transmission and reception of SPI4 data because Process, Voltage and Temperature variations can alter the alignment. The procedure is as follows (only shown for SPIA) * Enable the interrupts related to the high-speed receive interface block by writing FF to 30913. This would enable the status update on the register 3091C. It is also recommended to enable other interrupts as well. For example registers 30912 and 30914 so that the corresponding statuses can be monitored. * Set register 30910 to 0x71 this would set the DIP4 Error threshold to 7 and will enable baseline for SPIA to perform "ORSPI4 baseline" procedure. DIP4 Error threshold is set to 7 for experimental reasons only, most of the applications engineers would want to set it to 1 to flag any single DIP4 error. * Soft-reset the SPIA core by writing 0x02 to 30B20 and then clearing this bit. This can also be achieved by pulsing the s4a_fpga_reset FPGA/CORE interface pin. Please note that every time the ORSPI4 core is soft-reset the TXPDM contents are erased whereas the contents of RXPDM, RXCAL and TXCAL remain intact. Software engineers would want to put a state machine in the API to reprogram the TXPDM once the soft reset is pulsed. Soft reset may be required to pulse if because of any reason ORSPI4 loses its synchronization with another device. In that case "ORSPI4 baseline" procedure needs to be performed again by pulsing the soft reset. * Read the 3091C register - it should read 0x53 - Bit 0 = 0 indicates that the RDI PLL has locked to the REFCLKA. If the RDCLK (SPI4 receive clock) is present then the PLL will lock to the RDCLK. - Bit 1 = 1 indicates that the Baseline has been done - Bit 2 = 0 indicates that there are no Baseline errors - Bit 3 = 1 indicates that receive de-skew has been achieved. This bit will stay high if the enable training is not set in the register 30910, it will also be set once the training has been done. - Bit 4 = 0 indicates that there are no receive de-skew errors, these errors will only show up if the training has been enabled and de-skewing is not successful. - Bit 5 = 0 indicates that training is not detected - Bit 6 = 1 indicates that byte-lanes' alignment is off, this bit is also relevant if the training is enabled and Bytes are not being aligned properly. - Bit 7 = 1 indicates that the TX status is showing LOF, because the TX_CAL_M_MAIN and TX_CAL_LEN_MAIN do not match the RX_CAL_M_MAIN and RX_CAL_LEN_MAIN respectively. * Enable internal loopback by writing 0x08 to 30915. This is only required if there is no other SPI4 device talking to ORSPI4. External loopback can also be performed in which case this register bit should not be set. * Program the TX_DATA_MAX_T and TX_ALPHA values in the registers 30935, 30936, 30937, 30940, 30941 and 30942. Setting a non-zero value to these registers will automatically cause the transmit block to initiate the SPI4 training sequence. * Program the RX_FIFO_THRESHOLD_H (30911) and TX_FIFO_THRESHOLD_H (30945) values to 0x78 and 0x17 respectively. These are watermarks for internal asynchronous FIFOs. These are the recommended values. If MINBURST mode is desired then TX_FIFO_THRESHOLD_H needs to be set appropriately. Refer to MINBURST MODE section of the data sheet. * Keep baseline enabled and, enable training by writing 0x73 to 30910. * Read the 3091C register and it should read 0x55 - Bit 0 = 0 indicates that the receive PLL has locked to REFCLKA or RDCLK. - Bit 1 = 1 indicates that the Baseline has been done - Bit 2 = 0 indicates that there are no Baseline errors - Bit 3 = 1 indicates that RDI de-skew has been achieved - Bit 4 = 0 indicates that there are no RDI de-skew errors - Bit 5 = 1 indicates that training is detected. - Bit 6 = 0 indicates that byte-lanes' alignment is not off. - Bit 7 = 1 indicates that the TX status is showing LOF, because the TX_CAL_M_MAIN and
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ORCA ORSPI4 Data Sheet
TX_CAL_LEN_MAIN do not match the RX_CAL_M_MAIN and RX_CAL_LEN_MAIN respectively. * It is recommended that the training be kept enabled at all times so the dynamic alignment is performed to compensate for process, voltage and temperature variations. * Program the TX_CAL_M_MAIN equal to RX_CAL_M_MAIN and TX_CAL_LEN_MAIN equal to RX_CAL_LEN_MAIN and then the register 3091C should read 54. * Read register 3091D twice, the first value read could indicate DIP4 and DIP2 errors, if clears to 00 after the second read then there are no errors. The errors during the first read indicate that the errors existed before the training was performed. * Read the register 3090A to read the DIP4 error count. This register will keep counting if the bit 5 of 3091D is set, otherwise this register will show 00. * Read the register 3090B to read the DIP2 error count. This register will keep counting if the bit 6 of 3091D is set, otherwise this register will show 00. After the above configuration is completed, the device is not yet ready to transmit and receive data. The user still has to provision the Calendars and the Port Descriptor Memories for appropriate bandwidth. This is an indirect addressing mechanism where a single bit in register 30917 selects which memory space needs to be addressed. Once one of the bit is selected then the user can write to 31000 to 31FFF address space. The following example shows how to program TX PDM, RX PDM, TX calendar and RX calendar. * Four ports (0, 1, 2 and 3) of SPI4 data with equal bandwidth. * No DPRAM Partitions (Virtual FIFOs). * Write 20 HEX to 30917 to select the RX calendar indirect addressing * Next program the RX calendar memory through the following writes: - Write 00 to the 31000 location. - Write 01 to the 31001 location. - Write 02 to the 31002 location. - Write 03 to the 31003 location. * Write 10 HEX to register 30917 to select the RX PDM indirect addressing. Since there are no partitions for the DPRAMS, only the bits which correspond to the BANK_ID of the DPRAMs will be written. Bits that correspond to the PARTITION_ID of the DPRAMs are written to "000". - Write 00 HEX to the 31000 location which means that data will read from the DPRAM0 for port 0. - Write 08 HEX to the 31001 location which means that data will be read from the DPRAM1 for port 1. - Write 10 HEX to the 31002 location which means that data will be read from the DPRAM2 for port 2. - Write 18 HEX to the 31003 location which means that data will be read from the DPRAM3 for port 3. * Write 08 HEX to 30917 to select the TX calendar indirect addressing - Write 00 to the 31000 location. - Write 01 to the 31001 location. - Write 02 to the 31002 location. - Write 03 to the 31003 location. * Write 04 HEX to 30917 to select the TX PDM indirect addressing. TX PDM has a total of 6 fields to be written and they are divided into 3 bytes. These three bytes correspond to a single memory location for TX PDM, which has a total of 256 locations. - Write the port ID 00 HEX to 31000 corresponding to port 0. - Write 0F HEX to 31001 (000 to partition ID field and 1111 to BURST_VAL field). - Write 0C HEX to 31002 which implies: * MB_EN bit is set to `1' which means that MAX-BURST1 and MAX-BURST2 both will be supported, otherwise only MAX-BURST1 will be used. * M bit is set to `1' which means the port ID field programmed in the TX PDM is propagated to the FPGA on the
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ORCA ORSPI4 Data Sheet
SPIA_TXk_PORT_ID (k=32, 64, 128) signal. If M bit is not set then the port ID programmed in the TX calendar will be broadcast to the FPGA. * DPRAM BANK_ID field is set to "00". - Address location 31003 is not used. - Write 01 HEX to 31004 corresponding to port 1. - Write 0F HEX to 31005 (000 to partition ID field and 1111 to BURST_VAL field). - Write 0D HEX to 31006 (MB_EN bit is set to `1', M bit is set to `1' and DPRAM BANK_ID field is set to "01"). - Address location 31007 is not used. - Write 02 HEX to 31008 corresponding to port 2. - Write 0F HEX to 31009 (000 to partition ID field and 1111 to BURST_VAL field). - Write 0E HEX to 3100A (MB_EN bit is set to `1', M bit is set to `1' and DPRAM BANK_ID field is set to "10"). - Address location 3100B is not used. - Write 03 HEX to 3100C corresponding to port 3. - Write 0F HEX to 3100D (000 to partition ID field and 1111 to BURST_VAL field). - Write 0F HEX to 3100E (MB_EN bit is set to `1', M bit is set to `1' and DPRAM BANK_ID field is set to "10"). - Address location 3100F is not used. This concludes the configuration of the ORSPI4 SPIA Core in the dynamic mode. In LOW SPEED STATIC mode (bit 2 of register 30915 selected) and in LOW SPEED QUARTER RATE STATIC mode (bit 0 of register 30915 selected), the baseline procedure and the training procedure is not required. This means that the High Speed PLL is bypassed and therefore the BIT 0 of register 30910 will always be high. In static mode this is normal and should be ignored. In fact the only relevant bits in register 30910 are bits 6 and 7. If these bits are not high then that means ORSPI4 has hand-shaken with another device properly. Delay-Taps in STATIC mode After all the configuration procedure is performed, there is a possibility of ORSPI4 experiencing DIP-4 errors and RX alignment status flag being high. This can be tackled using two FPGA/CORE interface signals called SPI_DATM_A and SPI_DLYTAP_A [2:0]. With SPI_DATM_A set to high, SPI_DLYTAP_A[2:0] should be varied from 0 to 6 to adjust the RX data with respect to RDCLK to get a valid data eye. This would help getting rid of the DIP4 errors and the RX alignment status flag. This procedure is also a function of how the Board designer has laid out the 16 RX_DATA lanes. If all the lengths are grossly mismatched then this mechanism may not work, so it is imperative to design the board keeping the lengths of the RX_DATA as close as possible. SERDES Start-Up Sequence The following sequence is required by the SERDES. For information required for simulation that may be different than this sequence, see the ORSPI4 Design Kit. 1. Initiate a hardware reset by making RESETN low. Keep this low during FPGA configuration of the device. The device will be ready for operation 3 ms after the low to high transition of RESETN. 2. Configure the following SERDES internal and external registers. Note that after device initialization, all alarm and status bits should be read once to clear them. A subsequent read will provide the valid state. Set the following bits in register 30800: * Bits LCKREFN_[A:D] to "1", which implies lock to data. * Bits ENBYSYNC_[A:D] to "1" which enables dynamic alignment to comma. Set the following bits in register 30801: * Bits LOOPENB_[A:D] to "1" if high-speed serial loopback is desired. Set the following bits in registers 30002, 30012, 30022, 30032: * TXHR set to "1" if TX half-rate is desired.
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* 8B10BT set to "1" Set the following bits in registers 30003, 30013, 30023, 30033: * RXHR Set to "1" if RX half-rate is desired. * 8B10BR set to "1". * LINKSM set to "1" if the Fibre Channel state machine is desired.
ORCA ORSPI4 Data Sheet
Assert GSWRST bit by writing two "1"'s. Deassert GSWRST bit by writing two "0"s. Wait 3ms. If higher speed serial loopback has been selected, the receive PLLs will use this time to lock to the new serial data. Monitor the following alarm bits in registers 30000, 30010, 30020, 30030: * LKI, PLL lock indicator. "1" indicates that PLL has achieved lock. 3. If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three times: * K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma/) in FC mode. * /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI
Resets
Global Resets Global resets affect all blocks in the ORSPI4 Embedded ASIC Core (EAC) section (SPIA, SPIB, MC, MPI, and SERDES. A global reset can be caused by one the following: power-up reset, bitstream download without a partial reconfiguration enabled, hardware reset, or FPGA Global Set Reset (GSR).
Power-Up Reset The power-up reset process begins when the power supply voltage ramps up to approximately 80% of the nominal value of 1.5 V. Following this event, the device will be ready for normal operation after 3 ms. For more information on power-up reset, please refer to the ORCA SERIES 4 FPGA data sheet at www.latticesemi.com. Bitstream Download (DONE=0) During bitstream download, the FPGA DONE signal remains low until the part is fully configured During this time, all ORSPI4 EAC blocks remain in RESET. During partial reconfiguration, an FPGA register bit can be set to prevent a RESET of the EAC while DONE=0. For more information on bitstream configuration, please refer to the ORCA SERIES 4 FPGA data sheet at www.latticesemi.com. Hardware Reset (RESETN) A hardware reset is initiated by making the RESETN low for at least two microprocessor clock cycles. The device will be ready for operation 3 ms after the low to high transition of the RESETN. This reset function affects all EAC blocks. FPGA Global Set Reset (GSR) The FPGA Global Set Reset signal (GSR) can be made to reset the SPIA, SPIB and SERDES blocks of the ORSPI4 core. This can be done during the ORSPI4 Module/IP Generation phase of the ORSPI4 core in ispLEVER. During this phase, the "Disable GSR from resetting data path in FPSC Core" check button is left unchecked to enable GSR to reset these blocks. For more information on GSR, please refer to the ORCA SERIES 4 FPGA data sheet at www.latticesemi.com.
SPIA-only Resets The SPIA block can be individually reset though Software Reset-via the microprocessor interface, or using an FPGA interface signal.
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ORCA ORSPI4 Data Sheet
Software Reset (SOFT_RESET_S4A) A register bit used to reset the SPIA is SOFT_RESET_ S4A (30B20, bit 6). This bit, when set to "1", disables the SPIA block. FPGA Interface Reset (FPGA_RESET_S4A) FPGA_RESET_S4A performs the same function as SOFT_RESET_ S4A. The difference is that it is an FPGA interface signal instead of a configuration register bit.
SPIB-only Resets The SPIB block can be individually reset though Software Reset-via the microprocessor interface, or using an FPGA interface signal.
Software Reset (SOFT_RESET_S4B) A register bit used to reset the SPIB is SOFT_RESET_ S4B (30B20, bit 7). This bit, when set to "1", disables the SPIB block. FPGA Interface Reset (FPGA_RESET_S4B) FPGA_RESET_S4B performs the same function as SOFT_RESET_ S4B. The difference is that it is an FPGA interface signal instead of a configuration register bit.
MC-only Resets The Memory Controller (MC) block can be individually reset though Software Reset-via the microprocessor interface, or using an FPGA interface signal.
Software Reset (SOFT_RESET_MC) A register bit used to reset the MC is SOFT_RESET_ MC (30B20, bit 5). This bit, when set to "1", disables the MC block. FPGA Interface Reset (FPGA_RESET_MC) FPGA_RESET_MC performs the same function as SOFT_RESET_ MC. The difference is that it is an FPGA interface signal instead of a configuration register bit.
SERDES-only Resets The SERDES block can be individually reset though Software Reset-via the microprocessor interface, or using FPGA interface signals.
Software Reset (SWRST and HARD_RESET_FC) Using the software reset option via the microprocessor interface, each channel can be individually reset by setting SWRSTx (bit 2) to a logic "1" in the channel configuration register (30004,30014,30024,30034)). The device will be ready 3 ms after the SWRSTx bit is de-asserted. Similarly, all four channels per quad SERDES can be reset by setting the global reset bit GSWRST (30005, bit 2). The device will be ready for normal operation 3 ms after the GSWRST bit is de-asserted. Note that the software reset option resets only SERDES internal registers and counters. The microprocessor registers are not affected. It should also be noted that the embedded block couldn't be accessed until after FPGA configuration is complete. Also note that the SWRSTx and GSWRST are active when the corresponding memory map register bit is set high.
Another register bit used to reset the SERDES is HARD_RESET_FC (30B20, bit 4). This bit, when active, disables the SERDES and prevents any access to its internal microprocessor registers (300xx range).
FPGA Interface Reset signals (SYS_RST_N and FPGA_RESET_FC) FPGA_RESET_FC performs the same function as HARD_RESET_FC. The difference is that it is an FPGA interface signal instead of a configuration register bit.
SYS_RST_N is a synchronous active low reset FPGA interface signal. This signal, when active, resets the read side of the multi-channel alignment FIFOs.
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ORCA ORSPI4 Data Sheet
The following table describes the different methods of resetting various parts of the EAC. It lists the logic values set on the FPGA interface and the primary ASB pins.
Table 44. ORSPI4 RESET
ORSPI4 Core Affected Signal Name PWRUPRES = 1 DONE = 0 RESETN = 0 GSRN = 0 and GSRN_DISABLE = 0 FPGA_RESET_S4A = 1 SOFT_RESET_S4A = 1 FPGA_RESET_S4B = 1 SOFT_RESET_S4B = 1 FPGA_RESET_MC = 1 SOFT_RESET_MC = 1 FPGA_RESET_FC = 1 HARD_RESET_FC = 1 SYS_RST_N (Channel Alignment FIFO RESET) RESET Type FPGA signal FPGA I/O1 EAC IO FPGA signal Interface Signal Software Register Bit Interface Signal Software Register Bit Interface Signal Software Register Bit Interface Signal Software Register Bit Interface Signal
1
MPI * * *
SPIA * * * * * *
SPIB * * * *
M_CTRL * * * *
SERDES * * * *
* * * * * * *
1. Please refer to the ORCA SERIES 4 FPGA data sheet at www.latticesemi.com.
I/O TRI-STATE Functions
The EAC I/Os can be tri-stated using one of the three signals below.
TS_ALL This is an FPGA signal that globally tri-states all EAC IOs in addition to the FPGA IOs. For more information on TS_ALL, please refer to the ORCA SERIES 4 FPGA data sheet at http://www.latticesemi.com. TRISTN This is an ORSPI4 EAC active low IO that globally tri-states all EAC IOs. Power-Up In addition to its RESET function, power-up also puts the ORSPI4 FPSC IO in tri-state until the chip is fully powered up.
Power Down
When set low, the ORSPI4 FPSC "PDN" powers down the following: * all PLLs in the SPIA, SPIB, Memory Controller and SERDES * LVDS and HSTL buffers on the EAC section of the ORSPI4 * SPIA, SPIB, and SERDES logic
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ORCA ORSPI4 Data Sheet
ORSPI4 Memory Map
The ORSPI4 device features a variety of programming options which include all the OIF-SPI-4.2.0 specified configurable parameters. The base addresses for each functional block in the ORSPI4 device is shown in Figure 87 and Table 45. The SPIA and SPIB receive cores contain RAM blocks that are configured through writes to the address range 0x31000 - 0x317FF. Prior to configuring any of these memories, the user has to select one of the memories by writing into the appropriate memory select bit in address 0x30917 (SPIA) and 0x30A17 (SPIB). All interrupts on ORSPI4 are maskable and edge generated. Each interrupt source has a corresponding status latch bit that can be viewed as software status register bits. At the end of a status register read, both the status and edge-triggered interrupt register will be cleared. If the active interrupt condition still persists after the status register read, the status register will continue to show this condition but the edge-triggered interrupt register will remain clear not causing another interrupt. Every interrupt or status register bit has an interrupt enable bit that must be set to `1' to generate the associated interrupt or read the status. Each interrupt enable for the DPRAMs in SPIA and SPI4 blocks controls or enables eight interrupt sources. These enable registers are at register address 30912, 30943, (SPIA) 30A12, and 30A43 (SPIB). These 32 bits enable/disable 256 interrupts. All other interrupt enables are unique to an interrupt source. To make the interrupt structure user-friendly, two special top-level interrupt registers are provided. Each of the bits in these top-level interrupt registers point to specific functional blocks that caused an interrupt. The user can poll these top-level interrupt registers to check which block has caused an interrupt and then poll the relevant lowerlevel interrupts corresponding to a block. Each of the bits in the top-level interrupt status register 30B29 shown in Table 46 point to a specific functional block in the ORSPI4 device. Each of the bits in the SPIA or SPIB DPRAM toplevel interrupt status register 30B2A is the collective OR of its associated lower-level interrupts.
Figure 87. SPI4 Core Programming Addresses in ORSPI4
3xxxx Hex Address SYS_BUS SLAVE_IF
MEM_IF Configuration Memories
308XX
Control & Status registers To control SERDES Channels CORE_IF
309XX
Control & Status registers To control SPIA SPI4_IF
30AXX
Control & Status registers To control SPIB SPI4_IF
FPGA
Global
30BXX
COMM_IF
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Table 45. ORSPI4 Memory Space
Address (Hex) 3000x 3001x 3002x 3003x 308xx 3090x - 3092x 30930 - 3094x 30950 - 3097x 30980 - 3099x 31000 - 317FF 30100 - 3010F Description Channel A in SERDES, internal registers Channel B in SERDES, internal registers Channel C in SERDES, internal registers Channel D in SERDES, internal registers Channel registers outside the SERDES SPI4 Core A Control registers SPI4 Core A Status registers SPI4 Core B Control registers SPI4 Core B Status registers SPI4 Core A/B configurable RAM address space Memory Controller registers
Table 46. Top-level Interrupt Status Register 30B29
BIT 0 1 2 3 4 5 6 7 Interrupt Source SERDES Memory Controller Memory Controller DPRAM SPI_B_2 SPI_B_1 SPI_A_2 SPI_A_1 30B09 30B08 SPIA (3090C-3090F, 30918-3091B, 30928-3092F) SPIB (30A0C-3090F, 30A18-30A1B, 30A28-30A2F) 30A1C 30A1D 3091C 3091D Associated Registers 3000, 3010, 3020, 3030
Table 47 details the memory map for the FPSC portion of the ORSPI4 device. Addresses for the control registers for the FPGA portion of the device are detailed in the ORCA Series 4 datasheet. This table shows the databus oriented for the PPC interface. DB0 is the MSB, while DB7 is the LSB. If the user master interface is used to perform operations to the ASIC core then the databus must be used in the opposite notation, where DB7 is the MSB and DB0 is the LSB.
Table 47. Memory Map
(0x) Absolute Address 30000 30010 30020 30030 Reset Value (0x)
Bit [0] [1] [2:7]
Name Reserved LKI_x Reserved
Description
SERDES Alarm Registers (Read Only), x = [A, ...,D] 00 Receive PLL Lock Indication, Channel x. LKI_x = "1" indicates the receive PLL is locked.
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Table 47. Memory Map (Continued)
(0x) Absolute Address 30001 30011 30021 30031 Reset Value (0x) FF Reserved. Must be set to "1". Set to "1" on device reset.
ORCA ORSPI4 Data Sheet
Bit [0] [1] [2:7] [0]
Name Reserved MLKI_x Reserved TXHR_x
Description
SERDES Alarm Mask Registers (Read/Write), x = [A, ...,D]
Mask Receive PLL Lock Indication, Channel x.
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), x = [A, ...,D] 30002 30012 30022 30032 00 Transmit Half Rate Selection Bit, Channel x. When TXHR_x = "1", HDOUT_x's baud rate = (REFCLK*10) and TCK78 =(REFCLK/4); when TXHR_x=0, HDOUT_x's baud rate = (REFCLK*20) and TCK78=(REFCLK[A:B]/2). TXHR_x = 0 on device reset. Transmit Powerdown Control Bit, Channel x. When PWRDNT_x = "1", sections of the transmit hardware are powered down to conserve power. PWRDNT_x = 0 on device reset. Transmit Preemphasis Selection Bit 0, Channel x. PE0_x and PE1_x select one of three preemphasis settings for the transmit section. PEO_x=PE1_x = 0, Preemphasis is 0% PEO_x=1, PE1_x = 0 or PEO_x=0, PE1_x = 1, Preemphasis is 12.5% PEO_x=PE1_x = 1, Preemphasis is 25%. PEO_x=PE1_x = 0 on device reset. Transmit Half Amplitude Selection Bit, Channel x. When HAMP_x = "1", the transmit output buffer voltage swing is limited to half its normal amplitude. Otherwise, the transmit output buffer maintains its full voltage swing. HAMP_x = 0 on device reset. Reserved. Must be set to 0 Set to "0" on device reset. Transmit 8b/10b Encoder Enable Bit, Channel x. When 8b10bT_x = "1", the 8b/10b encoder in the transmit path is enabled. Otherwise, the data is passed unencoded. 8b10bT_x = "0" on device reset. 20 Receive Half Rate Selection Bit, Channel x. When RXHR_x ="1", HDIN_x's baud rate = (REFCLK*10) and RCK78=(REFCLK/4); when RXHR_x= "0", HDIN_x's baud rate = (REFCLK*20) and RCK78=(REFCLK/2). RXHR_x = "0" on device reset. Receiver Power Down Control Bit, Channel x. When PWRDNR_x = 1, sections of the receive hardware are powered down to conserve power. PWRDNR_x = "0" on device reset. Reserved. Must be set to "1". Set to "1" on device reset. Receive 8b/10b Decoder Enable Bit, Channel x. When 8b10bR = "1", the 8b/10b decoder in the receive path is enabled. Otherwise, the data is passed undeocded. 8b10bR_x = "0" on device reset. Link State Machine Enable Bit, Channel x. When LINKSM_x = "1", the receiver Fiber Channel link state machine is enabled. Otherwise, the Fibre Channel link state machine is disabled. NOTE: LINKSM_x is ignored when XAUI_MODE_x= "1". LINKSM_x = "0" on device reset.
[1]
PWRDNT_x
[2] [3]
PE0_x PE1_x
[4]
HAMP_x
[5] [6] [7]
Reserved Reserved 8b10bT_x
30003 30013 30023 30033
[0]
RXHR_x
[1]
PWRDNR_x
[2] [3]
Reserved 8b10bR_x
[4]
LINKSM_x
[5:7]
Reserved
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Table 47. Memory Map (Continued)
(0x) Absolute Address 30004 30014 30024 30034 Reset Value (0x) 40 Reserved. Must be set to "0" Set to "0" on device reset.
ORCA ORSPI4 Data Sheet
Bit [0] [1]
Name Reserved MASK_x
Description
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), x = [A, ...,D]
Transmit and Receive Alarm Mask Bit, Channel x. When MASK_x = "1", the transmit and receive alarms of a channel are prevented from generating an interrupt (i.e., they are masked or disabled). The MASK_x bit overrides the individual alarm mask bits in the Alarm Mask Registers. MASK_x = "1" on device reset. Transmit and Receive Software Reset Bit, Channel x. When SWRST_x = "1", this bit provides the same function as the hardware reset, except that all configuration register settings are unaltered. This is not a self-clearing bit. Once set, this bit must be manually set and cleared. SWRST_x = "0" on device reset. Transmit and Receive Test Enable Bit, Channel x. When TESTEN_x = "1", the transmit and receive sections are placed in test mode. The TestMode[4:0] bits in the Global Control Registers specify the particular test, and must also be set. NOTE: When the global test enable bit GTESTEN = "0", the individual channel test enable bits are used to selectively place a channel in test or normal mode. When GTESTEN = "1", all channels are set to test mode regardless of their TESTEN setting TESTEN_x = "0" on device reset. 44 Reserved Set to "0" on device reset. Global Mask. When GMASK = "1", the transmit and receive alarms of all channel in the SERDES quad are prevented from generating an interrupt (i.e., they are masked or disabled). The GMASK bit overrides the individual MASK_x bits. GMASK = "1" on device reset. Software reset bit. The GSWRST bit provides the same function as the hardware reset for the transmit and receive sections of all four channels, except that the device configuration settings are not affected when GSWRST is asserted. This is not a self-clearing bit. Once set, this bit must be manually set and cleared. The GSWRST bit overrides the individual SWRST_x bits. GSWRST = "0" on device reset. Powerdown Transmit Function. When GPWRDNT = "1", sections of the transmit hardware for all four channels of are powered down to conserve power. The GPWRDNT bit overrides the individual PWRDNT_x bits. GPWRDNT= "0" on device reset. Powerdown Receive Function. When GPWRDNR = "1", sections of the receive hardware for all four channels are powered down to conserve power. The GPWRDNR bit overrides the individual PWRDNR_x bits. GPWRDNR = "0" on device reset. Reserved, "1" on device reset. Test Enable Control. When GTESTEN = "1", the transmit and receive sections of all four channels are placed in test mode. The GTESTEN bit overrides the individual TESTEN_x bits. GTESTEN = "0" on device reset. 00 TestMode - See Test Mode section for settings
[2]
SWRST_x
[3:6] [7]
Reserved TESTEN_x
SERDES Global Control Registers (Read/Write) Acts on all four Channels in SERDES Quad A or SERDES Quad B. 30005 [0] [1] Reserved GMASK
[2]
GSWRST
[3]
GPWRDNT
[4]
GPWRDNR
[5] [6] [7]
Reserved Reserved GTESTEN
30006
[0:4] [5:7]
TestMode Reserved
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Table 47. Memory Map (Continued)
(0x) Absolute Address 30800 Reset Value (0x) 00
ORCA ORSPI4 Data Sheet
Bit [0]A [1]B [2]C [3]D [4]A [5]B [6]C [7][D]
Name ENBYSYNC[A:D]
Description ENBYSYNC[A:D] = "1" Enables Receiver Byte Synchronization for Channel x. ENBYSYNC[A:D] = "0" on device reset. LCKREFN[A:D]= "0" Locks the receiver PLL to ref reference clock for Channel x. LCKREFN[A:D]= "1" = Locks the receiver to data for Channel x. NOTE: When LCKREFN[A:D] = "0", the corresponding LKI_x bit is also zero. LCKREFN[A:D]= "0" on device reset. Enable Loopback Mode for Channel x. When LOOPEN[A:D]= "1", the transmitter high-speed output is looped back to the receiver high-speed input. This mode is similar to high-speed loopback mode enabled by TESTMODE[A:D] except that LOOPEN[A:D] disables the high-speed serial output. LOOPEN[A:D]= "0" on device reset. Word Align Disable Bit. When NOWDALIGN[A:D]= "1", receiver word alignment is disabled for Channel x. NOWDALIGN[A:D]= "0" on device reset.
Control Registers (Read/Write), x = [A, ...,D]
LCKREFN[A:D]
30801
[0]A [1]B [2]C [3]D
LOOPENB[A:D]
[4]A [5]B [6]C [7]D 30810 [0]A [1]B [2]C [3]D [4]A [5]B [6]C [7]D 30811
NOWDALIGN[A:D]
DOWDALIGN[A:D]
00
Word Realign Bit. When DOWDALIGN[A:D] transitions from "0" to "1", the receiver realigns on the next comma character for Channel x. DOWDALIGN[A:D]= "0" on device reset. Enable multi-channel alignment for Channel x. When FMPU_STR_EN[A:D]= "1", the corresponding channel participates in multichannel alignment. FMPU_STR_EN[A:D]= "0" on device reset. Sync mode for x 00 = No channel alignment 10 = Twin channel alignment 01 = Quad channel alignment Resync a Single Channel. When FMPU_RESYNC1[A:D] transitions from "0" to "1", the corresponding channel is resynchronized (the write and read pointers are reset). FMPU_RESYNC1[A:D]="0" on device reset. Resync a Pair of Channels. When FMPU_RESYNC2[1:2] transitions from a "0" to a "1", the corresponding channel pair is resynchronized. FFMPU_RESYNC2[1:2]= "0" on device reset. Resync a Four-Channel Group. When FMPU_RESYNC4 transitions from a "0" to a "1", the corresponding four-channel group is resynchronized. FMPU_RESYNC4= "0" on device reset. Controls use of XAUI link state machine in place of Fibre-Channel state machine. When XAUI_MODE= "1", all four channels in the SERDES quad enable their XAUI link state machines. (LINKSM_x bits are ignored). XAUI_MODE= "0" on device reset.
FMPU_STR_EN[A:D]
[0:1]A FMPU_SYNMODE[A: 00 [2:3]B D][0:1] [4:5]C [6:7]D [0]A [1]B [2]C [3]D FMPU_RESYNC1[A: 00 D]
30820
[4]A & FMPU_RESYNC2[1: 00 B 2] [5]C &D [6] FMPU_RESYNC4[1: 00 2] XAUI_MODE 00
[7]
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Table 47. Memory Map (Continued)
(0x) Absolute Address 30821 Reset Value (0x)
ORCA ORSPI4 Data Sheet
Bit [0]
Name NOCHALGN
Description Bypass channel alignment. NOCHALGN =1 causes bypassing of multichannel alignment FIFOs for the corresponding SERDES quad. NOCHALGN = "0" on device reset.
[1:3] [4:5] [6:7] 30830 [0:3] [4]
Reserved RCKSEL[0:1] TCKSEL[0:1] Reserved SCHAR_ENA 00 Set this to 1 to enable characterization mode for the SERDES. Characterization mode also requires inputs TESTMD[1:0]N=00, and FPGA interface pin, ENABLE_SPI4_B = "0". The outputs for the SERDES can be observed at the following ports: TBC311 PMID20 CV PMID21 BYTSYNC PMID22 WDSYNC PMID23 RBCO PMID24 RBC1 PMID25 LDOUT9 PMID26 LDOUT8 PMID 27 LDOUT7 PMID28 LDOUT6 PMID29 LDOUT5 PMID30 LDOUT4 PMID31 LDOUT3 PMID32 LDOUT2 PMID33 LDOUT1 PMID34 LDOUT0 PMID35 Set this to 1 to enable driving of low speed TX ports of the SERDES during characterization mode. The inputs used During this mode are: TBC PMIA15 LDIN9 PMIA14 LDIN8 PMIA13 LDIN7 PMIA11 LDIN6 PMIA9 LDIN5 PMAI8 LDIN4 PMIA7 LDIN3 PMIA6 LDIN2 PMIA5 LDIN1 PMIA4 LDIN0 PMIA2 Selects the channel to observe and control during SERDES characterization mode: 00 = A 01 = B 10 = C 11 = D 00 XAUI Status Register. Status of XAUI link state machine for Channel x 00--No synchronization. 01--No comma (see XAUI state machine) and at least 1 cell value detected 10--Synchronization done. 11--Not used. XAUISTAT_x[0:1] = 00 on device reset. 00 00 Source for RCK78 (00=A, 10=B, 01=C, 11=D) Source for TCK78 (00=A, 10=B, 01=C, 11=D)
[5]
SCHAR_TXSEL
[6:7]
SCHAR_CHAN
Status Registers (Read Only), x = [A, ...,D] 30804 [0:1]A XAUISTAT[A:D][0:1] [2:3]B [4:5]C [6:7]D
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Table 47. Memory Map (Continued)
(0x) Absolute Address 30805 Reset Value (0x) 00
ORCA ORSPI4 Data Sheet
Bit [0]A [1]B [2]C [3]D [4]A [5]B [6]C [7]D
Name DEMUXWAS[A:D]
Description Status of Word Alignment. When DEMUX_WAS[A:D] = "1", word alignment is achieved for Channel x. DEMUX_WAS[A:D]= "0" on device reset. Status of Channel Alignment. When CH248_SYNC[A:D] = "1", multi-channel alignment is achieved for Channel x. CH248_SYNC[A:D]= "0" on device reset.
CH248_SYNC[A:D]
30814
[0:2]
Reserved Multi-Channel Out-Of-Sync Status. When SYNC2[1:2] OOS= "1", dual-channel synchronization has failed. SYNC2[1:2] OOS on device reset. Multi-Channel Out-Of-Sync Status. When SYNC4_OOS= "1", quad-channel synchronization has failed. SYNC4_OOS= "0" on device reset.
[3]A&B SYNC2[1:2]OOSL [4]C& D [5] SYNC4OOS
[6:7] 30900 A 30A00 B 30901 A 30A01 B 30902 A 30A02 B 30903 A 30A03 B 30904 A 30A04 B 30905 A 30A05 30906 A 30A06 B [0:7] [0:5] [6:7] [0:7] [0:7] [0:5] [6:7] [0:7] [0:1]
Reserved RX_CAL_M_MAIN Reserved RX_CAL_LEN_MAIN 00 RX_CAL_LEN_MAIN 00 RX_CAL_M_SHD Reserved RX_CAL_LEN_SHD RX_CAL_LEN_SHD 00 00 Shadow calendar length for the RX status frame of SPI4. Upper 2 bits. Shadow calendar length for the RX status frame of SPI4. Lower 8 bits. Number of virtual FIFOs in RX DPRAM bank 0 00 = 1 FIFO 01 = 2 FIFOs 10 = 4 FIFOs 11 = 8 FIFOs Number of virtual FIFOs in RX DPRAM bank 1 Number of virtual FIFOs in RX DPRAM bank 2 Number of virtual FIFOs in RX DPRAM bank 3 00 Length of calendar sequence on the RX status frame (SPI4, main) This is the most significant 2 bits of 10 total. Length of calendar sequence on the RX status frame (SPI4, main). This is the least significant 8 bits of 10 total Number of times shadow calendar sequence is repeated between insertions of framing pattern for the RX side of SPI4. 00 Number of times calendar sequence is repeated between insertions of framing pattern (RX SPI4, main)
SPI4 Core RX Control Registers (Read and Write)
RX_DPRAM_0_NUM 00 FIFO
[2:3] [4:5] [6:7]
RX_DPRAM_1_NUM FIFO RX_DPRAM_2_NUM FIFO RX_DPRAM_3_NUM FIFO
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Table 47. Memory Map (Continued)
(0x) Absolute Address 30907 A 30A07 B Reset Value (0x) RX bank 0 aggregation mode 00 = 32 bit data 01 = 64 bit data 10 = 128 bit data 11 = not valid RX bank 1 aggregation mode RX bank 2 aggregation mode RX bank 3 aggregation mode
ORCA ORSPI4 Data Sheet
Bit [0:1]
Name
Description
RX_DPRAM_0_AGG 00 R_MODE
[2:3] [4:5] [6:7] 30910 A 30A10 B [0] [1:3] [4] [5] [6] [7] 30911 A 30A11 B 30912 A 30A12 B [0:7] [0:3] [4:7] 30913 A 30A13 B [0]
RX_DPRAM_1_AGG R_MODE RX_DPRAM_2_AGG R_MODE RX_DPRAM_3_AGG R_MODE Reserved RX_DIP4_ERR_TH RX_DISABLE_STAT US RX_MASK_DIP4 RX_EN_TRAINING RX_EN_BASELINE RX_FIFO_THRESHO 00 LD_H RX_DPRAM_FIFO_ OVERRUN_INT_EN RX_DPRAM_FIFO_U RRUN_INT_EN RX_PLL_LOL_INT_E 00 N RX_BAS_DONE_INT _EN 00 00
Number of consecutive bad/good DIP-4 code words for SPI4 RX to lose/gain alignment. Loss of alignment is indicated by RX_ALGN_OFF_STS Causes 11 word to be sent on RX status frame. In turn causes far-end TX to cancel all credits and send a training pattern. Allows SPI4 link to be used in presence of errors on data input. Enable detection of training patterns on the RX side. Enable RX baseline process High watermark threshold for async FIFO within RDP. These bits act as an enable for the status flags and the interrupts regarding overrun of the 4 RX DPRAM FIFO banks. These bits act as an enable for the status flags and the interrupts regarding underrun of the 4 RX DPRAM FIFO banks. This bit enables the status flag and the interrupt regarding loss of lock in the SPI4 core (high-speed macrocell) PLL. See RX_PLL_LOL_STS in register 3091C[A], 3091C[B]. This bit enables the status flag and the interrupt for the SPI4 core when RDI completes the baselining process. Baselining is the self-alignment power-up process that the macro does after it detects lock of the PLL. See RX_BAS_DONE_STS in register 3091C[A], 3091C[B]. This bit enables the status flag and the interrupt for the SPI4 core when RDI fails its internal self-alignment process. See RX_BAS_ERR_STS in register 3091C[A], 3091C[B]. This bit enables the status flag and the interrupt for the SPI4 core when RDI completes its dynamic alignment process. See RX_DSKW_DONE_STS in register 3091C[A], 3091C[B]. This bit enables the status flag and the interrupt for the SPI4 core when RDI fails to dynamically align. See RX_DSKW_ERR_STS in register 3091C[A], 3091C[B]. This bit enables the status flag and the interrupt for the SPI4 core when RDI detects training patterns. See RX_TRN_DET_STS in register 3091C[A], 3091C[B]. This bit enables the status flag and the interrupt for the SPI4 core loss of RX alignment due to excess consecutive DIP4 errors. See RX_ALGN_OFF_STS in register 3091C[A], 3091C[B]. This bit enables the status flag and the interrupt for the SPI4 core TX status from having too many consecutive DIP2 errors. See TX_STATUS_LOF_STS
[1]
[2]
RX_BAS_ERR_INT_ EN RX_DSKW_DONE_I NT_EN RX_DSKW_ERR_IN T_EN RX_TRN_DET_INT_ EN RX_ALGN_OFF_INT _EN TX_STATUS_LOF_IN T_EN
[3]
[4]
[5]
[6]
[7]
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Table 47. Memory Map (Continued)
(0x) Absolute Address 30914 A 30A14 B Reset Value (0x) 00
ORCA ORSPI4 Data Sheet
Bit [0] [1] [2] [3:4] [5] [6] [7]
Name Reserved Reserved RX_ILLEGAL_CTL_I NT_EN Reserved RX_DIP4_INT_EN TX_DIP2_INT_EN RX_ASYNC_FIFO_O VERRUN_INT_EN
Description
SPI4 Core TX/RX Control Registers (Read and Write)
This bit enables the status flag and the interrupt when the SPI4 receives unsupported extended control words. This bit enables the status flag and the interrupt for the SPI4 core RX detection of a DIP4 error. This bit enables the status flag and the interrupt for the SPI4 core TX detection of a status framing error (either DIP2 or unexpected 11 pattern). This bit enables the status flag and the interrupt for the SPI4 core asynchronous FIFO in RDP block being overrun. When set to `1', enables data rates of 100 - 200 Mbps. The PLLs in the transmit and receive SPI4 high-speed blocks are bypassed in this mode. This control enables far-end loopback when it is set to 1. Far-end loopback sends RDAT inputs back to TDAT outputs, sends RDCLK back to TDCLK, sends TSTAT back to RSTAT outputs, and ATSCLK back to RSCLK. Forces low speed data rates of (400-622 Mbits/s). The transmit PLL is still used to synthesize the SPI4 transmit clock TDCLK. However, the dynamic alignment block in the receive side is bypassed. No training sequences are used in low speed mode. `0' - Selects LVTTL I/O for SPI4 status `1' - Selects LVDS I/Os for SPI4 status (Full-rate LVDS status I/Os specified by OIF SPI4.0 is not supported). Enables loops from high-speed SPI4 TDAT outputs to RDAT inputs and RSTAT to TSTAT status inputs just before I/O. Enables near-end parallel loop from TDP to RDP blocks and RSP to TSP blocks bypassing the high-speed SPI4 interface logic blocks. Must enable SPI4_LOOPBK_HS for this to work. Causes TDP to send bad parity code words. Causes RSP to send bad parity code words.
30915 A 30A15 B
[0] [1]
SPI4_QUARTER_RA 00 TE SPI4_LOOPBK_FE
[2]
SPI4_LOW_SPEED_ DATA_SEL
[3]
SPI4_STATUS_IO_S EL SPI4_LOOPBK_HS SPI4_LOOPBK_LS
[4] [5]
[6] [7] 30916 A 30A16 B [0:2] [3] [4]
TX_FORCE_DIP4_E RR RX_FORCE_DIP2_E RR Reserved MIN_BURST_MODE 00 RX_CAL_SW_EN
Set minimum burst mode for transmit path Inserts the calendar select word after the frame sync pattern on the receive SPI4 status channel 0 = Selects main calendar for outgoing RX status frame (calendar select word will be "01") 1 = Selects shadow calendar (calendar select word will be "10") Detect the calendar select word after the frame sync pattern on the transmit status Mode control for managing the transmission of bursts when the DPRAM partition becomes empty in the middle of a burst. 0 =continue to try to access DPRAM for the remainder of burst. 1 = abort the burst.
[5]
RX_CAL_SEL
[6] [7]
TX_CAL_SW_EN TX_BURST_TERMIN ATION
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Table 47. Memory Map (Continued)
(0x) Absolute Address 30917 A 30A17 B Reset Value (0x)
ORCA ORSPI4 Data Sheet
Bit [0:1] [2]
Name Reserved
Description Enables calendar memory for SPI4 RX calendar to be written via MPI. The RX_CAL memory encompasses address ranges 0 to 2047. Addresses 0 to 1023 are for the main calendar; addresses 1024 to 2047 are for the shadow calendar. SPI4 RX Calendar memory is write only. Enables memory for SPI4 RX port descriptors to be read or written via MPI. Addresses 0 to 255 valid for this memory. Each location contains 3 unused bits, 2 BANK_ID bits and 3 PARTITION_ID bits. Enables calendar memory for SPI4 TX calendar to be written via MPI. The TX_CAL memory encompasses address ranges 0 to 2047. Addresses 0 to 1023 are for the main calendar; addresses 1024 to 2047 are for the shadow calendar.SPI4 TX Calendar memory is write only. Enables memory for SPI4 TX port descriptors to be read or written via MPI. The valid address range is 0 to 1023. The least significant 2 address bits are used as byte enables. 00 accesses the PORT_ID (8 bits) 01 accesses PARTITION_ID (3 bits), an unused bit and BURST_VAL (4 bits) 10 accesses 4 unused bits, MB_EN (1 bit), M (1 bit), and BANK_ID (2 bits). The upper 8 bits of address represent the port number being configured. Enables read and write access to TX credits via MPI. The valid memory address range is 0 to 511. The credit for each port is a 10-bit entity. The upper 8 of 9 bits of address select which port to read or write. The lowest bit of address acts as a byte select as follows: 0 accesses the least significant 8 bits of the credit field 1 accesses the most significant 2 bits (right-justified) of the credit field Enables memory for SPI4 TX status to be read or written via MPI. This memory used address ranges 0 to 255. Each location has six left-most bits unused and two status bits. Full level select for all partitions within bank [0:3]. Valid for 32-bit, 64-bit and 128-bit mode. 0 = truly full 1 = 3/4 FIFO lines full +1. E.g.: For a FIFO size of 32, this value will be (3/4 * 32) + 1 = 25 lines. Each line in the FIFO is always 128 bits of data irrespective of the aggregation mode Empty level select for all partitions within bank [0:3]. Valid for 32-bit, 64-bit and 128-bit mode. 0 = truly empty 1 = 1/4 full - 1. E.g.: For a FIFO size of 32, this value will be (1/4 * 32) - 1 = 7 lines. Each line in the FIFO is always 128 bits of data irrespective of the aggregation mode
RX_CAL_MEM_SEL 00
[3]
RX_PDM_MEM_SEL
[4]
TX_CAL_MEM_SEL
[5]
TX_PDM_MEM_SEL
[6]
TX_CRED_MEM_SE L
[7]
TX_STAT_MEM_SEL
30920 A 30A20 B
[0:3}
TX_DPRAM_FULL_T 00 YPE_SEL
[4:7]
RX_DPRAM_EMPTY _TYPE_SEL
SPI4 Core TX Control Registers (Read and Write) 30921 A 30A21 B 30922 A 30A22 B 30923 A 30A23 30924 A 30A24 B [0:7] [0:5] [6:7] [0:7] [0:7] TX_CAL_M_MAIN Reserved TX_CAL_LEN_MAIN 00 TX_CAL_LEN_MAIN TX_CAL_M_SHD 00 Length of main calendar sequence on the TX status frame. These are the most significant 2 bits of 10 total. Length of main calendar sequence on the TX status frame. These are the least significant 8 bits of 10 total. Number of times the transmit shadow calendar sequence is repeated between insertions of framing pattern. 00 Number of times the transmit main calendar sequence is repeated between insertions of framing pattern.
164
Lattice Semiconductor
Table 47. Memory Map (Continued)
(0x) Absolute Address 30925 A 30A25 B 30926 30A26 30927 A 30A27 B Reset Value (0x) 00
ORCA ORSPI4 Data Sheet
Bit [0:5] [6:7] [0:7] [0:1]
Name Reserved TX_CAL_LEN_SHD TX_CAL_LEN_SHD
Description Shadow calendar length for the transmit status frame of SPI4. Upper 2 bits Shadow calendar length for the transmit status frame of SPI4. Lower 8 bits Number of virtual FIFOs in TX DPRAM bank 0 00 = >1 FIFO 01 = >2 FIFOs 10 = >4 FIFOs 11 = >8 FIFOs Number of virtual FIFOs in TX DPRAM bank 1 Number of virtual FIFOs in TX DPRAM bank 2 Number of virtual FIFOs in TX DPRAM bank 3 TX bank 0 aggregation mode 00 = 32 bit data 01 = 64-bit data 10 = 128-bit data 11 = not valid TX bank 1 aggregation mode TX bank 2 aggregation mode TX bank 3 aggregation mode
TX_DPRAM_0_NUM 00 FIFO
[2:3] [4:5] [6:7] 30930 A 30A30 B [0:1]
TX_DPRAM_1_NUM FIFO TX_DPRAM_2_NUM FIFO TX_DPRAM_3_NUM FIFO TX_DPRAM_0_AGG 00 R_MODE
[2:3] [4:5] [6:7] 30931 A 30A31 B 30932 A 30A32 30933 A 30A33 B 30934 A 30A34 B 30935 A 30A35 B 30936 A 30A36 B 30937 A 30A37 B 30940 A 30A40 B [0:5] [6:7] [0:7] [0:5] [6:7] [0:7] [0:7]
TX_DPRAM_1_AGG R_MODE TX_DPRAM_2_AGG R_MODE TX_DPRAM_3_AGG R_MODE Reserved TX_MAX_BURST1 TX_MAX_BURST1 Reserved TX_MAX_BURST2 TX_MAX_BURST2 TX_DATA_MAX_T (byte a) TX_DATA_MAX_T (byte b) TX_DATA_MAX_T (byte c) TX_DATA_MAX_T (byte d) 00 00 00 00
Maximum number of 16-byte bursts expected for any port when its status is STARVING. These are the 2 most significant bits of a 10-bit number Maximum number of 16-byte bursts expected for any port when its status is STARVING. These are the 8 least significant bits of a 10-bit number Maximum number of 16-byte bursts expected for any port when its status is HUNGRY. These are the 2 most significant bits of a 10-bit number Maximum number of 16-byte bursts expected for any port when its status is HUNGRY. These are the 8 least significant bits of a 10-bit number Maximum interval between training sequences on the transmit data interface. A 32-bit number is formed from 4 bytes organized as {a, b, c, d} and read left to right. When this number is "0", training sequences are disabled. Maximum interval between training sequences on the transmit data interface. A 32-bit number is formed from 4 bytes organized as {a, b, c, d} and read left to right. When this number is "0", training sequences are disabled. Maximum interval between training sequences on the transmit data interface. A 32-bit number is formed from 4 bytes organized as {a, b, c, d} and read left to right. When this number is "0", training sequences are disabled. Maximum interval between training sequences on the transmit data interface. A 32-bit number is formed from 4 bytes organized as {a, b, c, d} and read left to right. When this number is "0", training sequences are disabled.
[0:7]
00
[0:7]
00
[0:7]
00
165
Lattice Semiconductor
Table 47. Memory Map (Continued)
(0x) Absolute Address 30941 A 30A41 B 30942 A 30A42 B 30943 A 30A43 B Reset Value (0x) 00
ORCA ORSPI4 Data Sheet
Bit [0:7]
Name TX_ALPHA (byte a)
Description Number of times training sequence needs to be repeated every TX_DATA_MAX_T cycles. The number is formed from 2 TX_ALPHA bytes, in the order {a,b}. Number of times training sequence needs to be repeated every TX_DATA_MAX_T cycles. The number is formed from 2 TX_ALPHA bytes, in the order {a,b}. These bits act as enables for the status flags and the interrupts regarding an overrun of the 4 TX DPRAM FIFO banks. These bits act as enables for the status flags and the interrupts regarding an underrun of the 4 TX DPRAM FIFO banks. Number of consecutive bad/good DIP-2 code words for SPI4 TX to lose/gain alignment. Loss of alignment is indicated by TX_STATUS_LOF_STS Low watermark threshold for sync input FIFO within TDP. This is used only if MIN_BURST_MODE is set. Depending on the number of lines in a burst, this threshold should be set to integer[(BURST_VAL/4) + 1] High watermark threshold for async FIFO within TDP to declare a full condition. This causes writes to the TDP to be held off; meaning that an overrun condition can not occur here.
[0:7]
TX_ALPHA (byte b)
00
[0:3] [4:7]
TX_DPRAM_FIFO_O 00 VERRUN_INT_EN TX_DPRAM_FIFO_U 00 RRUN_INT_EN Reserved TX_DIP2_ERR_TH 00
30944 A 30A44 B 30945 A 30A45 B
[0:4] [5:7] [0:2]
TX_FIFO_THRESHO 00 LD_L TX_FIFO_THRESHO LD_H
[3:7]
SPI4 Core RX/TX Spare Controls (Read and Write) 30946 A 30A46 B 30908 A 30A08 B 30909 A 30A09 B 3090A A 30A0A B 3090B A 30A0B B [0:7] [0:7] Reserved Reserved 00 00
SPI4 Core Status Registers (Read Only) [0:7] [0:7] [0:7] Reserved RX_DIP4_ERR_CNT 00 TX_DIP2_ERR_CNT 00 RX_DPRAM_0_FIFO 00 _OVERRUN_STS Count of DIP4 errors. Count will reset to "0" on a read of this register. If count reaches maximum (255) it will hold. Count of status framing errors. See SIP2_ERR_STS. Count will reset to "0" after a read of this register. If count reaches maximum (255) it will hold. Overrun status of bank 0 DPRAM FIFOs 0 to 7. These are enabled by RX_DPRAM_FIFO_OVERRUN_INT_EN[0] (register 30912[A], 30A12[B]). These bits clear when read, but will set immediately if the error condition persists. Overrun status of bank 1 DPRAM FIFOs 0 to 7. These are enabled by RX_DPRAM_FIFO_OVERRUN_INT_EN[1] (register 30912[A], 30A12[B]). These bits clear when read, but will set immediately if the error condition persists. Overrun status of bank 2 DPRAM FIFOs 0 to 7. These are enabled by RX_DPRAM_FIFO_OVERRUN_INT_EN[2] (register 30912[A], 30A12[B]). These bits clear when read, but will set immediately if the error condition persists. Overrun status of bank 3 DPRAM FIFOs 0 to 7. These are enabled by RX_DPRAM_FIFO_OVERRUN_INT_EN[3] (register 30912[A], 30A12[B]). These bits clear when read, but will set immediately if the error condition persists. Underrun status of bank 0 DPRAM FIFOs 0 to 7. These are enabled by RX_DPRAM_FIFO_URRUN_INT_EN[0] (register 30912[A], 30A12[B]). These bits clear when read, but will set immediately if the condition persists.
3090C A [0:7] 30A0C B
3090D A [0:7] 30A0D B
RX_DPRAM_1_FIFO 00 _OVERRUN_STS
3090E A 30A0E B
[0:7]
RX_DPRAM_2_FIFO 00 _OVERRUN_STS
3090F A 30A0F B
[0:7]
RX_DPRAM_3_FIFO 00 _OVERRUN_STS
30918 A 30A18 B
[0:7]
RX_DPRAM_0_FIFO 00 _URRUN_STS
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Lattice Semiconductor
Table 47. Memory Map (Continued)
(0x) Absolute Address 30919A 30A19B 3091A A 30A1A B 3091B A 30A1B B Reset Value (0x)
ORCA ORSPI4 Data Sheet
Bit [0:7]
Name
Description Underrun status of bank 1 DPRAM FIFOs 0 to 7. These are enabled by RX_DPRAM_FIFO_URRUN_INT_EN[1] (register 30912[A], 30A12[B]). These bits clear when read, but will set immediately if the condition persists. Underrun status of bank 2 DPRAM FIFOs 0 to 7. These are enabled by RX_DPRAM_FIFO_URRUN_INT_EN[2] (register 30912[A], 30A12[B]). These bits clear when read, but will set immediately if the condition persists. Underrun status of bank 3 DPRAM FIFOs 0 to 7. These are enabled by RX_DPRAM_FIFO_URRUN_INT_EN[3] (register 30912[A], 30A12[B]). These bits clear when read, but will set immediately if the condition persists. Status flag for loss of lock in PLL within the SPI4 receive core. This flag is enabled by RX_PLL_LOL_INT_EN (register 30913[A], 30A13[B]). Status flag for SPI4 receive core completing the baselining process. Baselining is the self-alignment power-up process that the macro does after it detects lock of the PLL. This flag is enabled by RX_BAS_DONE_INT_EN. (register 30913[A], 30A13[B]) Status flag for SPI4 receive core failing its internal self-alignment process. This flag is enables by RX_BAS_INT_EN (register 30913[A], 30A13[B]). Status flag for SPI4 receive dynamic alignment complete. This flag is enabled by RX_DSKW_DONE_INT_EN. Status flag for SPI4 receive core failing to dynamically align. This flag is enabled by RX_DSKW_ERR_INT_EN (register 30913[A], 30A13[B]). Status flag for SPI4 receive core detecting training patterns. This flag is enabled by RX_TRN_DET_INT_EN (register 30913[A], 30A13[B]). Status flag for loss of data alignment due to excess consecutive DIP4 errors. This flag is enabled by RX_ALIGN_OFF_INT_EN (register 30913[A], 30A13[B]). Status flag for TX status frame having too many consecutive DIP2 errors. This flag is enabled by TX_STATUS_LOF_INT_EN (register 30913[A], 30A13[B]).
RX_DPRAM_1_FIFO 00 _URRUN_STS RX_DPRAM_2_FIFO 00 _URRUN_STS RX_DPRAM_3_FIFO 00 _URRUN_STS RX_PLL_LOL_STS RX_BAS_DONE_ST S 00
[0:7]
[0:7]
3091C A [0] 30A1C B [1]
[2] [3] [4] [5] [6]
RX_BAS_ERR_STS RX_DSKW_DONE_S TS RX_DSKW_ERR_ST S RX_TRN_DET_STS RX_ALGN_OFF_ST S TX_STATUS_LOF_S TS Reserved RX_ILLEGAL_CTL_ STS Reserved RX_DIP4_ERR_STS 00 TX_DIP2_ERR_STS RX_ASYNC_FIFO_O VERRUN_STS TX_DPRAM_0_FIFO 00 _OVERRUN_STS 0
[7]
3091D A [0:1] 30A1D B [2] [3:4] [5] [6] [7]
Status flag indicating that an illegal control work was received
Status flag for DIP4 error Flag for error in framing TSTAT[0:1] inputs. This can be an unexpected 11 pattern or a DIP2 error. Status flag for RX FIFO overrun inside S4RDP block.
SPI4 Core TX Status Registers (Read and Write) 30928 A 30A28 B [0:7] Overrun status of bank 0 TX DPRAM FIFOs 0 to 7. These are enabled by TX_DPRAM_FIFO_OVERRUN_INT_EN[0]. These bits clear when read, but will set immediately if the condition persists. This will happen when writing to the DPRAM FIFOs while SPI[A,B]_k_FIFO_FULL_j is high. Overrun status of bank 1 TX DPRAM FIFOs 0 to 7. These are enabled by TX_DPRAM_FIFO_OVERRUN_INT_EN[1]. These bits clear when read, but will set immediately if the condition persists. This will happen when writing to the DPRAM FIFOs while SPI[A,B]_k_FIFO_FULL_j is high.
30929 A 30A29 B
[0:7]
TX_DPRAM_1_FIFO 00 _OVERRUN_STS
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Lattice Semiconductor
Table 47. Memory Map (Continued)
(0x) Absolute Address 3092A A 30A2A B Reset Value (0x)
ORCA ORSPI4 Data Sheet
Bit [0:7]
Name
Description Overrun status of bank 2 TX DPRAM FIFOs 0 to 7. These are enabled by TX_DPRAM_FIFO_OVERRUN_INT_EN[2]. These bits clear when read, but will set immediately if the condition persists. This will happen when writing to the DPRAM FIFOs while SPI[A,B]_k_FIFO_FULL_j is high. Overrun status of bank 3 TX DPRAM FIFOs 0 to 7. These are enabled by TX_DPRAM_FIFO_OVERRUN_INT_EN[3]. These bits clear when read, but will set immediately if the condition persists. This will happen when writing to the DPRAM FIFOs while SPI[A,B]_k_FIFO_FULL_j is high. Underrun status of bank 0 DPRAM FIFOs 0 to 7. These are enabled by TX_DPRAM_FIFO_URRUN_INT_EN[0]. These bits clear when read, but will set immediately if the condition persists. Underrun status of bank 1 DPRAM FIFOs 0 to 7. These are enabled by TX_DPRAM_FIFO_URRUN_INT_EN[1]. These bits clear when read, but will set immediately if the condition persists. Underrun status of bank 2 DPRAM FIFOs 0 to 7. These are enabled by TX_DPRAM_FIFO_URRUN_INT_EN[2]. These bits clear when read, but will set immediately if the condition persists. Underrun status of bank 3 DPRAM FIFOs 0 to 7. These are enabled by TX_DPRAM_FIFO_URRUN_INT_EN[3]. These bits clear when read, but will set immediately if the condition persists. This 4-bit number sets the threshold for the MC_WFIFO_FULL flag for the write data FIFO. Example: if the field is 0100, then the MC_WFIFO_FULL flag will be raised when there are 4 (or fewer) filled slots remaining in the FIFO. This 4-bit number sets the threshold for the MC_RFIFO_EMPTY flag for the read data FIFO. Example: if the field is 1010, then the MC_RFIFO_EMPTY flag will be raised when there are 10 (or fewer) filled slots remaining in the FIFO.
TX_DPRAM_2_FIFO 00 _OVERRUN_STS
3092B A 30A2B B
[0:7]
TX_DPRAM_3_FIFO 00 _OVERRUN_STS
3092C A [0:7] 30A2C B 3092D A [0:7] 30A2D B 3092E A 30A2E B 3092F A 30A2F B [0:7]
TX_DPRAM_0_FIFO 00 _URRUN_STS TX_DPRAM_1_FIFO 00 _URRUN_STS TX_DPRAM_2_FIFO 00 _URRUN_STS TX_DPRAM_3_FIFO 00 _URRUN_STS
[0:7]
Memory Controller Control Registers (Read and Write) 30B00 [0:3] MC_FULL_THRESH 00 OLD
[4:7]
MC_EMPTY_THRES HOLD
30B01
[0]
MC_RD_DFIFO_UR RUN_INT_EN MC_RD_IFIFO_URR UN_INT_EN MC_WR_DFIFO_UR RUN_INT_EN MC_WR_IFIFO_URR UN_INT_EN MC_RD_DFIFO_OV ERRUN_INT_EN MC_RD_IFIFO_OVE RRUN_INT_EN MC_WR_DFIFO_OV ERRUN_INT_EN MC_WR_IFIFO_OVE RRUN_INT_EN
00
Enable for Memory Controller read data FIFO underrun status flag MC_RD_DFIFO_URRUN_STS, and associated interrupt MEM_CTRL1_INT. Enable for Memory Controller read instruction FIFO underrun status flag MC_RD_IFIFO_URRUN_STS, and associated interrupt MEM_CTRL1_INT. Enable for Memory Controller write data FIFO underrun status flag MC_WR_DFIFO_URRUN_STS, and associated interrupt MEM_CTRL1_INT. Enable for Memory Controller write instruction FIFO underrun status flag MC_WR_IFIFO_URRUN_STS, and associated interrupt MEM_CTRL1_INT. Enable for Memory Controller read data FIFO overrun status flag MC_RD_DFIFO_OVERRUN_STS, and associated interrupt MEM_CTRL1_INT. HW_Issue 23 indicates this should never happen. Enable for Memory Controller read instruction FIFO overrun status flag MC_RD_IFIFO_OVERRUN_STS, and associated interrupt MEM_CTRL1_INT. Enable for Memory Controller write data FIFO overrun status flag MC_WR_DFIFO_OVERRUN_STS, and associated interrupt MEM_CTRL1_INT. Enable for Memory Controller write instruction FIFO overrun status flag MC_WR_IFIFO_OVERRUN_STS, and associated interrupt MEM_CTRL1_INT.
[1] [2]
[3] [4]
[5]
[6]
[7]
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Lattice Semiconductor
Table 47. Memory Map (Continued)
(0x) Absolute Address 30B02 Reset Value (0x)
ORCA ORSPI4 Data Sheet
Bit [0:6] [7]
Name Reserved MC_ID_ERR_INT_E N MC_BURST_MODE Reserved MC_ICK_SEL
Description Enable for incoherent data and instruction words status flag MC_ID_ERR_STS, and associated interrupt MEM_CTRL2_INT.
30B03
[0] [1] [2:3]
00
0 = 2-word burst 1 = 4-word burst Input clock selector: 00 = MCREFCLK (HSTL) 01 = BTREFCLK (SPIA reference, LVTTL) 10 = ATREFCLK (SPIB reference, LVTTL) 11 = F_MC_REFCLK (FPGA)
[4:6] [7]
Reserved MC_OCK_SEL 00 Selects between input clock divided by 2, or PLL output for source of PMIC/PMICN: 0 = input clock 1 = PLL Numerator of multiplier factor for frequency of PLL output clock: CK2X = MC_ICK * (PLL_N / PLL_M) Denominator of multiplier factor for frequency of PLL Output clock: CK2X = MC_ICK * (PLL_N / PLL_M)
30B04
[0] [1:3] [4] [5:7]
Reserved PLL_N Reserved PLL_M Reserved Reserved MC_RD_DFIFO_UR RUN_STS MC_RD_IFIFO_URR UN_STS MC_WR_DFIFO_UR RUN_STS MC_WR_IFIFO_URR UN_STS MC_RD_DFIFO_OV ERRUN_STS MC_RD_IFIFO_OVE RRUN_STS MC_WR_DFIFO_OV ERRUN_STS MC_WR_IFIFO_OVE RRUN_STS Reserved MC_ID_ERR_STS Reserved 00 Status flag for incoherent data and instruction words. Enabled by MC_ID_ERR_INT_EN. 00 Status flag for read data FIFO underrun. Enabled by MC_RD_DFIFO_URRUN_INT_EN Status flag for read instruction FIFO underrun. Enabled by MC_RD_IFIFO_URRUN_INT_EN Status flag for write data FIFO underrun. Enabled by MC_WR_DFIFO_URRUN_INT_EN Status flag for write instruction FIFO underrun. Enabled by MC_WR_IFIFO_URRUN_INT_EN Status flag for read data FIFO overrun. Enabled by MC_RD_DFIFO_OVERRUN_INT_EN Status flag for read instruction FIFO overrun. Enabled by MC_RD_IFIFO_OVERRUN_INT_EN Status flag for write data FIFO overrun. Enabled by MC_WR_DFIFO_OVERRUN_INT_EN Status flag for write instruction FIFO overrun. Enabled by MC_WR_IFIFO_OVERRUN_INT_EN 00 00
30B05 30B06 30B08
[0:7} [0:7] [0] [1] [2] [3] [4] [5] [6] [7]
Memory Controller Status Registers (Read Only)
30B09
[0:6] [7]
30B0A
[0:7]
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Lattice Semiconductor
Table 47. Memory Map (Continued)
(0x) Absolute Address 30B20 Reset Value (0x)
ORCA ORSPI4 Data Sheet
Bit [0:3] [4] [5] [6] [7]
Name Reserved HARD_RESET_FC SOFT_RESET_MC SOFT_RESET_S4A SOFT_RESET_S4B COM_SPARE_C FORCE_INT Reserved SERDES_INT
Description
Common Control Registers (Read and Write) 00 Hard reset for SERDES block. When set to 1, disabled SERDES logic by resetting it. Same functionality as interface signal FPGA_RESET_FC Software reset for Memory Controller block Software reset for SPIA block Software reset for SPIB block 00 Spare common control bits Force all the enabled status and interrupt bits Reserved 00 Signals that an enabled interrupt has come from the SERDES. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from the Memory Controller other than the FIFOs. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from the Memory Controller FIFOs. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from one of the DPRAM FIFO banks. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from the register 30A1D. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from register 30A1C. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from register 3091D. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from register 3091C. This is cleared when read and will only reassert when the underlying event goes away and comes back.
30B21
[0:6] [7]
Common Status Registers (Read and Write) 30B28 30B29 [0:7] [0]
[1]
MEM_CTRL2_INT
[2]
MEM_CTRL1_INT
[3]
DPRAM_INT
[4]
SPI_B_COR2_INT
[5]
SPI_B_COR1_INT
[6]
SPI_A_COR2_INT
[7]
SPI_A_COR1_INT
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Lattice Semiconductor
Table 47. Memory Map (Continued)
(0x) Absolute Address 30B2A Reset Value (0x) 00
ORCA ORSPI4 Data Sheet
Bit [0]
Name TX_INT_B
Description Signals that an enabled interrupt has come from TX DPRAM FIFOs for SPI4 core B. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from RX DPRAM FIFOs for SPI4 core B. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from TX DPRAM FIFOs for SPI4 core A. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from RX DPRAM FIFOs for SPI4 core B. This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from DPRAM bank 3 FIFOs (or both SPI4 blocks, both TX and RX flags). This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from DPRAM bank 2 FIFOs (or both SPI4 blocks, both TX and RX flags). This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from DPRAM bank 1 FIFOs (or both SPI4 blocks, both TX and RX flags). This is cleared when read and will only reassert when the underlying event goes away and comes back. Signals that an enabled interrupt has come from DPRAM bank 0 FIFOs (or both SPI4 blocks, both TX and RX flags). This is cleared when read and will only reassert when the underlying event goes away and comes back.
[1]
RX_INT_B
[2]
TX_INT_A
[3]
RX_INT_A
[4]
BANK_3_INT
[5]
BANK_2_INT
[6]
BANK_1_INT
[7]
BANK_0_INT
30B2B 31000
[0:7] [0:7]
COM_SPARE_S data[7:0]
00 00
Spare common status bits Embedded control memories are accessed when register addresses 310031FFF are written or read. The address passed to the embedded memories is the lower 12 bits of the register address. Writing to a register address in this range causes data to be transferred to the selected embedded memories. More than one memory can be written with a single operation by having multiple select bits active. The select bits are 30917 and 30A17 registers. Reading from a register address in this range causes the data in the memory selected to appear. The following priority rules apply to the selection of which memory is read from. (1) 30917 bits take precedence over bits in the 30A17 register. (2) lower bit numbers take precedence over higher bit numbers within a register.
Embedded Control Memory Access (31000-31FFF)
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. The ORCA Series 4 FPSCs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress
Table 48. Absolute Maximum Ratings.
Parameter Storage Temperature Power Supply Voltage with Respect to Ground Symbol TSTG VDD33 VDD33_FPGAPLL VDD15 VDDIO SPI4 Voltages with respect to Ground VDDA_SPIA VDDA_SPIB VDDA_SPIC VDDA_SPID Memory Controller Voltages with respect to Ground SERDES Supply Voltages FPGA Input Signal with Respect to Ground FPGA Signal Applied to High-impedance Output Maximum Package Body (Soldering) Temperature VDDH VDD_PLL VDD_ANA VDDGB VIN -- -- Min. -65 - 0.3 -0.3 -0.3 - 0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VSS - 0.3 VSS - 0.3 -- Max. 150 4.2 4.2 2.0 4.2 2.0 2.0 2.0 2.0 2.0 4.2 2.0 2.0 VDDIO + 0.3 VDDIO + 0.3 220 Unit C V V V V V V V V V V V V V V C
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Recommended Operating Conditions
Table 49. Recommended Operating Conditions
Parameter Power Supply Voltage with respect to Ground1 Symbol VDD33 VDD33_FPGAPLL VDD15 SPI4 Voltages with respect to Ground VDDA_SPIA VDDA_SPIB VDDA_SPIC VDDA_SPID Memory Controller Voltages with respect to Ground VDDH
2
Min. 3.0 3.0 1.425 1.425 1.425 1.425 1.425 1.425 0.64 0.64 0.64 0.64 3.0 1.425 1.425 1.425 1.425 Vss-0.3 Vss-0.3 - 40
Max. 3.6 3.6 1.575 1.575 1.575 1.575 1.575 1.575 0.87 0.87 0.87 0.87 3.6 1.575 1.575 1.89 1.89 VDDIO to +0.3 1.89 125
Unit V V V V V V V V V V V V V V V V V V V C
REF_1 REF_2 REF_3 REF_4 VDDA_PLL SERDES Supply Voltage SERDES CML I/O Supply Voltages FPGA Input Voltage Memory Controller Input Voltage2 Junction Temperature VDD_ANA VDDGB VDDIB VDDOB V_IN V_IWMCTRL TJ
1. For FPGA Recommended Operating Conditions and Electrical Characteristics, see the Recommended Operating Conditions and Electrical Characteristics tables in the ORCA Series 4 FPGA data sheet (OR4E06) and the ORCA Series 4 I/O Buffer Technical Note. 2 Memory Controller 1.8V tolerant with VDDH = 1.5V 5%
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
ORSPI4 Power Tables
Table 50. ORSPI4 Post-configuration Standby Current
Clock Frequency Parameter Post-configuration Standby Current VDD15* 500 VDD33* 300 VDDH 200 Unit mA
* Conditions: TA = 85C, VDD15 = 1.575V, VDD33 = 3.6V, VDDIO = 3.6V, internal oscillator running, no output loads, inputs VDDIO or VSS. Standby current is tested with the embedded core in a powered down state.
Table 51. ORSPI4 Combined SPIA and SPIB Worst Case Power Table
Reference Clock Frequency 112.5 MHz 0.887 81.25 MHz 0.570 77.75 MHz 0.513 200 MHz 0.082 156 MHz 0.017 0.407 0.424 W 0.436 0.518 W 0.493 1.006 W 0.486 1.056 W 0.518 1.405 W VDD15 VDDA_SPI[A:D] Power* VDD33 Power* Power per SPI Interface*
Parameter Frequency Total
Unit
450 MHz (900 Mbps) with Dynamic Alignment
325 MHz (650 Mbps) with Static Alignment Frequency Total 311 MHz (622 Mbps) with Static Alignment Frequency Total 100 MHz (200 Mbps) Quarter Rate Frequency Total 78 MHz (156 Mbps) Quarter Rate Frequency Total
* Power measured with both SPIA and SPIB operating simultaneously. AC power only. Power numbers do not include post-configuration standby current (see Table 50). FPGA power not included. FPGA power is application dependent - See the ORCA Series 4 Data Sheet to calculate FPGA power. Conditions: TA = 85C, VDD15 = 1.575V, VDD33 = 3.6V, VDDIO = 3.6V.
Table 52. ORSPI4 QDR Memory Controller Worst Case Power Table
Parameter Clock Frequency VDD15, VDDH Power VDD33 Power Total Power Value 160 226.8 46.8 273.6 Unit MHz mW mW mW
Note: In many applications the PLL can be disabled to reduce power. Temperature: -40C to 125C, Power Supplies: VDD15, VDDH = 1.575V, VDD33 = 3.6V, Data Pattern: PRBS 2^31-1
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Table 53. ORSPI4 SERDES Worst Case Power Table
Parameter SERDES, MUX/DEMUX, Align FIFO and I/O (per channel) SERDES, MUX/DEMUX, Align FIFO and I/O (per channel) SERDES, MUX/DEMUX, Align FIFO and I/O (per channel) 8b/10b Encoder/Decoder (per channel) Operating Frequency 1.25 GHz 2.5 GHz 3.125 GHz 3.125 GHz
ORCA ORSPI4 Data Sheet
VDD151, 2 195 210 225 50
Units mW mW mW mW
1. With all channels operating, Temperature: -40C to 125C, Power Supplies: VDD_ANA, VDDIB, VDDOB = 1.575V, Data Pattern: PRBS 2^31-1 2. With ORSPI4 CML output buffers connected to ORSPI4 CML input buffers. Actual power dissipation can vary depending on the termination used.
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ORCA ORSPI4 Data Sheet
SPI4 Electrical and Timing Characteristics
SPI4 LVDS I/O
Table 54. Driver DC Data*
Parameter Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage Output Offset Voltage Output Impedance, Differential RO Mismatch Between A and B Change in Differential Voltage Between Complementary States Change in Output Offset Voltage Between Complementary States Output Current Output Current Power-off Output Leakage Symbol VOH VOL VOD VOS Ro RO VOD VOS ISA, ISB ISAB |Ixa|, |Ixb| Test Conditions RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% VCM = 1.0 V and 1.4 V VCM = 1.0 V and 1.4 V RLOAD = 100 1% RLOAD = 100 1% Driver shorted to GND Drivers shorted together VDD = 0 V VPAD, VPADN = 0 V--2.5 V Min. -- 0.925 0.25 1.125* 80 -- -- -- -- -- --
Typ. -- -- -- -- 100 -- -- -- -- -- --
Max. 1.475 -- 0.45 1.275 120 10 25 25 24 12 10
Units V V V V W % mV mV mA mA mA
1. VDD33 = 3.1 V--3.5 V, VDD15 = 1.4 V--1.6 V, -40 C. 2. External reference, REF10 = 1.0 V 3%, REF14 = 1.4 V 3%.
Table 55. Receiver DC Data1
Parameter
Input Voltage Range, VIA or VIB Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance
1. VDD = 3.1V - 3.5V, 0 C - 125 C.
Symbol
VI VIDTH VHYST RIN
Test Conditions
VGPD < 925 mV DC - 1 MHz VGPD < 925 mV 450 MHz (+VIDTHH) - (-VIDTHL) With build-in termination, center-tapped
Min.
0.0 -100 25 80
Typ.
1.2 -- -- 100
Max.
2.4 100 -- 120
Units
V mV mV
Table 56. SPI4 LVDS Operating Parameters
Parameter
Transmit Termination Resistor Receiver Termination Resistor
Test Conditions
-- --
Min.
80 80
Normal
100 100
Max.
120 120
Units
. .
Note: Under worst-case operating conditions, the LVDS driver will withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. Similarly, when outputs are short-circuited to each other or to ground, the LVDS will not suffer permanent damage. The LVDS driver supports hot insertion. Under a well-controlled environment, the LVDS I/O can drive backplane as well as cable.
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Lattice Semiconductor
Figure 88. Output Buffer Delays
ts[i] out[i] PAD OUT PAD OUT
ORCA ORSPI4 Data Sheet
3pF
3pF
Table 57. LVDS Driver AC Data1
Parameter VOD Fall Time, 80% to 20% VOD Rise Time, 20% to 80% Differential Skew |tPHLA - tPLHB| or |tPHLB - tPLHA| Symbol tF tR tSKEW1 Test Conditions ZL = 100 1% CPAD = 3.0 pF, CPAD = 3.0 pF ZL = 100 1% CPAD = 3.0 pF, CPAD = 3.0 pF Any differential pair on package at 50% point of the transition Min. 100 100 -- Typ. -- -- -- Max. 210 210 50 Units ps ps ps
1. VDD33 = 3.1V - 3.5 V, VDD15 = 1.4V - 1.6 V, -40C.
Termination Resistor The LVDS drivers and receivers operate at 100 differential impedance, as shown below. External resistors are not
required. The differential driver and receiver buffers include termination resistors inside the device package, as shown in Figure 89 below. The center tap inputs should be connected to ground via a .01 pF capacitor.
Figure 89. SPI4 LVDS Driver and Receiver and Associated Internal Components
LVDS Driver
LVDS Receiver
50 100
Center Tap
50
External Device Pins
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Lattice Semiconductor SPI4 AC Timing
ORCA ORSPI4 Data Sheet
Supported Data Rates The SPI4 interfaces (SPIA and SPIB) on the ORSPI4 device support the following data rates
Table 58. Supported Data Rates
Clock Frequency (DDR) 250 - 450 MHz 250 - 325 MHz 50 - 100 MHz Transmit REFCLK Frequency 62.5 - 112.5 MHz 62.5 - 81.25 MHz 100 - 200 MHz1 Static Quarter-rate static mode
Data Rate 500 -900 Mbps 500 -650 Mbps 100 - 200 Mbps
Recommended Operating Mode Dynamic
1 SPI[A,B]_TREFCLK_x8 internal signal is used in quarter-rate mode
SPI4.2 Data Interface
System Timing Reference Points Figure 90 shows the system timing reference points A and B for the data path timing parameters for both the transmit interface and the receive interface.
Figure 90. System Timing Reference Points.
A TDAT[15:0] / RDAT[15:0} TCTL/RCTL B
Source
TDCLK/RDCLK
Sink
Figure 91 defines the timing parameters tdia and tdib which show the relationship of TDCLK to TDAT generated by the ORSPI4 transmit interface. Values of tdia and tdib are given in Table 59.
Figure 91. SPI4.2 Transmit Timing Points with Respect to Clock Edge
Launch Edge (A) TDCLK
D TDCLK
TDAT
T dia T dib
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Table 59. SPI4.2 Transmit Data Interface Timing
Symbol tdia tdib DTDCLK Description ORSPI4 transmit data (TDAT[15:0], TCTL) invalid window before clock edge (Source A) ORSPI4 transmit data (TDAT[15:0], TCTL) invalid window after clock edge (Source A) TDCLK duty cycle Min -- -- 45%
ORCA ORSPI4 Data Sheet
Max 0 400 55%
Units ps ps TDCLK Period
Figure 92 defines the timing parameters ts and th which show the setup and hold requirements at the ORSPI4 receive interface when in static mode, which are dependent on the SPI_DLYTAP register settings chosen. Values of ts and th at all values of SPI_DLYTAP are given in Table 60.
Figure 92. SPI4.2 Receive Timing Points with Respect to Clock Edge
Capture Edge (B) RDCLK
RDAT
SPI_DLYTAP_A,B[2:0]=0
tS
tH
SPI_DLYTAP_A,B[2:0]=4
tS
tH
SPI_DLYTAP_A,B[2:0]=7
tS tH
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Table 60. SPI4.2 Receive Data Interface Timing
Symbol Description ORSPI4 Receive data setup time with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=0 ORSPI4 Receive data setup time with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=1 ORSPI4 Receive data setup time with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=2 ORSPI4 Receive data setup time with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=3 ORSPI4 Receive data setup time with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=4 ORSPI4 Receive data setup time with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=5 ORSPI4 Receive data setup time with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=6 ORSPI4 Receive data setup time with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=7 ORSPI4 Receive data hold with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=0 ORSPI4 Receive data hold with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=1 ORSPI4 Receive data hold with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=2 ORSPI4 Receive data hold with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=3 ORSPI4 Receive data hold with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=4 ORSPI4 Receive data hold with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=5 ORSPI4 Receive data hold with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=6 ORSPI4 Receive data hold with respect to clock capture edge (Sink B) SPI_DLYTAP_A,B[2:0]=7
Note: Receive data = RDAT[15:0], RCTL.
ORCA ORSPI4 Data Sheet
Min 60
Max --
Units ps
-20
--
ps
-80
--
ps
-150
--
ps
tS
-220
--
ps
-280
--
ps
-360
--
ps
-430
--
ps
790
--
ps
870
--
ps
970
--
ps
1050
--
ps
tH
1120
--
ps
1210
--
ps
1290
--
ps
1370
--
ps
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
The static timing budget for a data transfer between two ORSPI4 devices at a data rate of 650 Mbps in shown in Table 61.
Table 61. Data Path Interface Timing Example for Static Alignment (ORSPI4 to ORSPI4)
Description TDCLK/RDCLK frequency Before reference point A1 Between reference points A and B After reference point B Clock to data skew, clock duty cycle distortion, data duty cycle distortion, data jitterTdia + Tdib Data to data skew, relative jitter Subtotal Gmax Device setup and hold Sampling Error Total Total 650 Mbps bit period Available margin
Note 1: ORSPI4 Transmit Specification Note 2: ORSPI4 Receive Specification
2
Value 325 400 100 500 940 50 1490 1540 50
Unit MHz ps ps ps ps ps ps ps ps
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
The dynamic alignment timing budget for a data transfer between two ORSPI4 devices is shown in Table 62.
Table 62. Data Path Parameters for Dynamic Alignment.
Description Transmit clock jitter Transmit data jitter with respect to clock edge Receive clock jitter tolerance Value (UI peak-to-peak) 0.11 0.09 0.60
With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, 900 Mbit/s data rate with 112.5 Mhz REFCLK, REFCLK jitter of 30 ps, TJ = -40 C to 125 C, 1.425 V to 1.575 V supply. Jitter measured with a Wavecrest SIA-3000.
SPI4.2 Status Interface
System Timing Reference Points Figure 93 shows the system timing reference points A and B for status channel timing parameters listed in Table 63.
Figure 93. Status Channel Reference Points
D TSTAT[1:0] / RSTAT[1:0] C
Source
TSCLK/RSCLK
Sink
Note: Only status signals are shown
Figure 94. Status Channel Reference Points with Respect to Clock Edge (LVDS and LVTTL I/Os)
Launch Edge (C) RSCLK
RSTAT
T dia Tdib
Capture Edge (D) TSCLK
TSTAT
ts
th
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Table 63. Status Path Interface ORSPI4 Timing in Centered (OIF) Mode
OIF-SPI4-02.0 Specification Requirements Symbol fD fS -- tdia tdib Description TDCLK/RDCLK frequency TSCLK/RSCLK frequency TSCLK/RSCLK duty cycle RSTAT invalid with respect to clock edge (Reference point C) RSTAT invalid with respect to clock edge (Reference point C) Setup time for TSTAT with respect to TSCLK LVTTL Buffers (Reference point D) Setup time for TSTAT with respect to TSCLK LVDS Buffers (Reference point D) Hold time for TSTAT with respect to TSCLK LVTTL Buffers (Reference point D) Hold time for TSTAT with respect to TSCLK LVDS Buffers (Reference point D) Min -- -- 40 -- -- 2.0 -- 0.5 -- Max 450 112.5 60 2.5 1.0 -- -- -- --
ORCA ORSPI4 Data Sheet
ORSPI4 Timing in Centered (OIF) Mode Min -- -- 40 -- -- 1.0 1.0 0.5 0.7 Max 450 112.5 60 0.30 0.45 -- -- -- -- Units MHz MHz % ns ns ns ns ns ns
tS
tH
Note: This table compares the OIF Specification requirements vs. the ORSPI4 Specification. There is no OIF Specification for LVDS buffers.
Figure 95. ORSPI4 Static Mode Status Signals Data Capture (Reference Point D)
0 D
TSTAT/ RSTAT
LVTTL
1
LVDS
STATUS_IO_SEL Reference Point D SPI_STAM
0
0 1
TSCLK/ RSCLK
LVTTL
1
LVDS
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ORCA ORSPI4 Data Sheet
Figure 96. Status Channel Reference Points with Respect to Clock Edge (Edge Aligned Legacy Mode)
Launch Edge (C) RSCLK
RSTAT
T dia T dib
Capture Edge (D) TSCLK
TSTAT
ts
th
Table 64. Status Path Interface ORSPI4 Timing in Legacy Mode
ORSPI4 Timing in Legacy Mode Symbol fD fS -- tdia tdib Description TDCLK/RDCLK frequency TSCLK/RSCLK frequency TSCLK/RSCLK duty cycle Data invalid window with respect to clock edge (Reference point C) Data invalid window with respect to clock edge (Reference point C) Setup time for TSTAT with respect to TSCLK LVTTL Buffers (Reference point D) Setup time for TSTAT with respect to TSCLK LVDS Buffers (Reference point D) Hold time for TSTAT with respect to TSCLK LVTTL Buffers (Reference point D) Hold time for TSTAT with respect to TSCLK LVDS Buffers (Reference point D) 40 -- -- 0.5 0.7 1.2 1.0 Min Max 450 112.5 60 0.3 0.45 -- -- -- -- Units MHz MHz % ns ns ns ns ns ns
tS*
tH*
Note: This table compares the OIF Specification requirements vs. the ORSPI4 Specification. There is no OIF Specification for LVDS buffers.
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ORCA ORSPI4 Data Sheet
SERDES Electrical and Timing Characteristics
SERDES High Speed Data Transmitter
Table 65 specifies serial data output buffer parameters measured on devices with typical and worst case process parameters and over the full range of operation conditions.
Table 65. Serial Output Timing and Levels (CML I/O)
Parameter Rise Time (20%--80%) Fall Time (80%--20%) Common Mode Differential Swing (Full Amplitude) Output Load (external)
1
Min. 50 50 VDDOB - 0.30 600 300 --
Typ. 80 80 VDDOB - 0.25 700 350 86
Max. 110 110 VDDOB - 0.15 1000 500 --
Units ps ps V mVp-p mVp-p .
Differential Swing (Half Amplitude)1
1. Differential swings are measured at the end of 3 inches of FR-4 and 12 inches of coax cable.
Transmitter output jitter is a critical parameter to systems with high-speed data links. Table 66 and Table 67 specify the transmitter output jitter for typical and worst case devices over the full range of operating conditions.
Table 66. Channel Output Jitter (3.125 Gbits/s)
Parameter Deterministic Random Total2, 3 Min. -- -- -- Typ.1 0.13 0.06 0.19 Max.1 0.24 0.12 0.36 Units UIp-p UIp-p UIp-p
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., 0oC to 85oC, 1.425 V to 1.575 V supply. 2. Wavecrest SIA-3000 instrument used to measure one-sigma (rms) random jitter component value. This value is multiplied by 14 to provide the peak-to-peak value that corresponds to a BER of 10-12. 3. Total jitter measurement performed with Wavecrest SIA-3000 at a BER of 10-12. See instrument documentation and other Wavecrest publications for a detailed discussion of jitter types included in this measurement.
Table 67. Channel Output Jitter (2.5 Gbits/s)
Parameter Deterministic Random Total2, 3 Min. -- -- -- Typ.1 0.12 0.06 0.18 Max.1 0.15 0.16 0.31 Units UIp-p UIp-p UIp-p
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., 0oC to 85oC, 1.425 V to 1.575 V supply. 2. Wavecrest SIA-3000 instrument used to measure one-sigma (rms) random jitter component value. This value is multiplied by 14 to provide the peak-to-peak value that corresponds to a BER of 10-12. 3. Total jitter measurement performed with Wavecrest SIA-3000 at a BER of 10-12. See instrument documentation and other Wavecrest publications for a detailed discussion of jitter types included in this measurement.
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Lattice Semiconductor SERDES High Speed Data Receiver
ORCA ORSPI4 Data Sheet
Table 68 specifies receiver parameters measured on devices with worst case process parameters and over the full range of operation conditions.
Table 68. External Data Input Specifications
Parameter Input Data Stream of Nontransitions Sensitivity (differential), worst-case Input Levels2 Internal Buffer Resistance (Each input to VDDIB) PLL Lock Time3
1
Conditions 8b/10b encode/decode off 3.125 Gbps -- -- --
Min. -- 80 VSS - 0.3 40 --
Typ. -- -- -- 50 --
o o
Max. 72 -- VDD_ANA + 0.3 60 Note 3
Units Bits mVp-p V . --
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0 C to 85 C, 1.425 V to 1.575 V supply. 2. Input level min + (input peak to peak swing)/2 common mode input voltage input level max - (input peak to peak swing)/2 3. The ORSPI4 SERDES receiver performs four levels of synchronization on the incoming serial data stream, providing first bit, then byte (character), then channel (32-bit word), and finally optional multi-channel alignment as described in TN1025. The PLL Lock Time is the time required for the CDR PLL to lock to the transitions in the incoming high-speed serial data stream. If the PLL is unable to lock to the serial data stream, it instead locks to REFCLK to stabilize the voltage-controlled oscillator (VCO), and periodically switches back to the serial data stream to again attempt synchronization.
Input Data Jitter Tolerance A receiver's ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface standards have recognized the dependency on jitter type and have recently modified specifications to indicate tolerance levels for different jitter types as they relate to specific protocols (e.g XAUI, FC, Infiniband etc.). Sinusoidal jitter is considered to be a worst case jitter type. Table 69 shows receiver specifications with 10 MHz sinusoidal jitter injection. XAUI specific jitter tolerance measurements were measured in a separate experiment detailed in technical note TN1032, SERDES Test Chip Jitter, and are not reflected in these results.
Table 69. Receiver Sinusoidal Jitter Tolerance Specifications
Parameter Input Data Jitter Tolerance @ 3.125 Gbps, Typical Jitter Tolerance @ 3.125 Gbps, Worst case Jitter Tolerance @ 2.5 Gbps, Typical Jitter Tolerance @ 2.5 Gbps, Worst case 600 mV diff eye1 600 mV diff eye 600 mV diff eye
1
Conditions
Max. 0.75 0.65 0.79 0.67
Unit UIP-P UIP-P UIP-P UIP-P
600 mV diff eye1
1
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0oC to 85oC, 1.425 V to 1.575 V supply. Jitter measured with a Wavecrest SIA-3000.
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ORCA ORSPI4 Data Sheet
Input Eye-Mask Characterization Figure 97 provides an eye-mask characterization of the SERDES receiver input. The eye-mask is specified below for two different eye-mask heights. It provides guidance on a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Almost all detrimental characteristics of transmit signal and the interconnection link design result in eye-closure. This, combined with the eyeopening limitations of the line receiver, can provide a good indication of a link's ability to transfer data error-free. The Clock and Data Recovery (CDR) portion of the ORSPI4 SERDES receiver has the ability to filter incoming signal jitter that is below the clock recovery PLL bandwidth (about 3 MHz). The eye-mask specifications of Table 70 are for jitter frequencies above the PLL bandwidth of the CDR, which is a worst case condition. When jitter occurs at frequencies below the PLL bandwidth, the receiver jitter tolerance is significantly better. For this case error-free data detection can occur even with a completely closed eye-mask.
Figure 97. Receive Data Eye-Diagram Template (Differential)
T
1.2 V
V
H
UI
Table 70. Receiver Eye-Mask Specifications1
Parameter Input Data Eye Opening Width (H) @ 3.125 Gbps Eye Opening Width (T) @ 3.125 Gbps Eye Opening Width (H) @ 3.125 Gbps Eye Opening Width (T) @ 3.125 Gbps Eye Opening Width (H) @ 2.5 Gbps Eye Opening Width (T) @ 2.5 Gbps Eye Opening Width (H) @ 2.5 Gbps Eye Opening Width (T) @ 2.5 Gbps V=175 mV diff1 V=175 mV diff1 V=600 mV diff V=175 mV diff V=600 mV diff
1
Conditions
Value 0.55 0.15 0.35 0.10 0.42 0.15 0.33 0.10
Unit UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P UIP-P
V=600 mV diff1
1
V=175 mV diff1
1
V=600 mV diff1
1. With PRBS 2^7-1 data pattern, 10 MHz sinusoidal jitter, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0oC to 85oC, 1.425 V to 1.575 V supply.
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Lattice Semiconductor SERDES External Reference Clock
ORCA ORSPI4 Data Sheet
The external reference clock selection and its interface are a critical part of system applications for this product. Table 71 specifies reference clock requirements, over the full range of operating conditions. The designer is encourage to read TN1040, SERDES Reference Clock, which discusses various aspects of this system element and its interconnection.
Table 71. Reference Clock Specifications (REFCLKP and REFCLKN)
Parameter Frequency Range Frequency Tolerance1 Duty Cycle (Measured at 50% Amplitude Point) Rise Time Fall Time P-N Input Skew Differential Amplitude Common Mode Level Single-Ended Amplitude Input Capacitance (at REFCLKP) Input Capacitance (at RECLKN) Min. 60 -350 40 -- -- -- 500 Vsingle-ended/2 250 -- -- Typ. -- -- 50 500 500 -- 800 0.75 400 -- -- Max. 185 350 60 1000 1000 75 2 x VDDIB VDD15 - (Vsingle-ended/2) VDDIB 5 5 Units MHz ppm % ps ps ps mVp-p V mVp-p pF pF
1. This specification indicates the capability of the high-speed receiver CDR PLL to acquire lock when the reference clock frequency and incoming data rate are not synchronized.
SERDES Core Timing Characteristics
Table 72 summarizes the end-to-end latencies through the embedded core for the various modes. All latencies are given in clock cycles for system clocks at half the REFCLK_[A:B] frequency. For a REFCLK_[A:B] of 156.25 MHz, a system clock cycle is 6.4 ns.
Table 72. Signal Latencies, Embedded Core
Operating Mode Transmit Path Receive Path Multi-Channel Alignment Bypassed1 With Multi-Channel Alignment1 4.5 clock cycles 13.5-22.5 clock cycles Signal Latency (max.) 5 clock cycles
1. With multi-channel alignment, the latency is largest when the skew between channels is at the maximum that can be correctly compensated for (18 clock cycles). The latency specified in the table is for data from the channel received first.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Memory Controller Electrical and Timing Characteristics
HSTL Class I and Class II
HSTL (High-Speed Transceiver Logic) - JEDEC standard JES 8-6 (August 1995), is a technology independent interface standard for digital integrated circuits. It is a voltage scalable and technology independent I/O structure. The I/O structures required by this standard contain a reference receiver (typically 50% of the VDDH), described as a REFI for single-ended inputs and outputs using power supply inputs (VDDH) that may differ from those operating the device itself. This buffer is designed to receive HSTL signal levels from devices wtih1.5V HSTL I/Os. HSTL also allows chips with different power supplies to easily communicate with each other.
Table 73. HSTL Class II DC Operating Specifications
Class Parameter VDDH REFI1 VTERM1 VIH VIL Class 1 Class 2 VOH2 VOL VOH2 VOL Condition -----IOH > 8 mA IOL > -8 mA IOH > 16 mA IOL > -16 mA Min 1.425 0.64 -REFI + 100mV -0.3 VDDH - 0.4 -VDDH - 0.4 -Typical 1.5 0.75 0.75 0.85 0.65 1.1 -1.1 -Max 1.575 0.87 VDDH + 0.3 REFI -100 mV -0.4 -0.4 Unit V V V V V V V V V
1. 50% VDDH 2. VDDH - 400 mV.
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Lattice Semiconductor
Figure 98. HSTL Termination Scheme
VDDH (1.5V) VDDMEM_IO 2
ORCA ORSPI4 Data Sheet
75 ohm
PMIK(N) &
HSTL-II Output Buffer
Z = 50 ohm
VTERM =
VDDH 2
VDDMEM_IO 2 VDDMEM_IO (1.5V)
PMIC(N) Signals
75 ohm
Z = 50 ohm
REFI = VDDH 2
VDDH (1.5V)
VDDMEM_IO 2
PMID, PMIA, PMIWN, PMIRN & PMIQ
50 ohm
HSTL-II Output Buffer
25 ohm Z = 50 ohm VDDMEM_IO 2 VTERM = VDDH 2 VDDMEM_IO (1.5V)
50 ohm
Signals
REFI = VDDH 2
Z = 50 ohm
EXT_1K ORSPI4 QDR Memory Device *
* Refer to memory specification for specific terminations 1.5 Kohm
Note: Refer to Technical Note TN1046 for more detailed board design guidelines for the ORSPI4 QDR Memory Controller.
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Supported Data Rates The Memory Controller on the ORSPI4 device can support the following data rates.
Table 74. Supported Data Rates (36-Bit QDR-II, 32 bit Considered Data)
Data Rate -1 Clock Frequency (DDR) 156 MHz Data Rate1, 2 19.97 Gbps
3
-2 Clock Frequency (DDR) Data Rate 165 MHz
1, 2 3
-3 Clock Frequency (DDR) 175 MHz Data Rate1, 2 22.40 Gbps3 21.12 Gbps
1. Data Rate = (Max. write data rate + Max. read data rate) for 32 bits of data. 2. Characterized with 200 Mhz rated QDR-II SRAM devices with their DLL enabled. Duty cycle of PMIC and PMICN signals was close to 50%. 3. Assumes board trace lengths of 3 inches or less.
Memory Controller Input/Output Timing Specification
Figure 99. Memory Controller Output Timing Specifications
PMIK
DPMIK(N)
PMIKN
Tav Tai
PMIA
Tdv T di
PMID
Table 75. Memory Controller Output Timing Specifications
Symbol tai tav tdi tdv DPMIK(N) Description PMIK to previous address invalid PMIK to address valid PMIK to previous data invalid PMIK to data valid PMIK/PMINKN duty cycle Min Value 1.2 2.0 1.0 2.65 40% Max Value - - - - 60% Units ns ns ns ns PMIK/PMIKN Clock Cycle
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Lattice Semiconductor
Figure 100. Memory Controller Input Timing Specifications
ORCA ORSPI4 Data Sheet
PMIC
PMICN
PMIQ
T rs Trh Tfs T rs
Table 76. Memory Controller Input Timing Specifications
Symbol trs trh tfs tfh Description PMIQ data in setup with respect to PMIC clock rising edge PMIQ data in hold with respect to PMIC clock rising edge PMIQ data in setup with respect to PMICN clock rising edge PMIQ data in hold with respect to PMICN clock rising edge Min Value -0.5 2.0 -0.5 2.0 Units ns ns ns ns
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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Power Supplies for ORSPI4
Power Supply Descriptions
Table 77 shows the ORSPI4 FPGA and embedded core power supply groupings. VDD33 Is a 3.3V positive power supply used for 3.3 V configuration RAMs. VDD33_FPGAPLL is a 3.3V positive power supply for internal PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on the board for proper operation. The five VDDIO supplies are positive power supply used by the FPGA I/O banks. The 1.5 volt digital power supplies are used for the FPGA and the embedded core transmit and receive digital logic including the microprocessor logic. The 1.5 volt analog power supply is used for SERDES high-speed analog circuitry in the embedded core between the I/O buffers and the digital logic. The SERDES VDDIB and VDDOB power supplies can be independently set to 1.5 V or 1.8 V, depending on the end application. The SERDES guard band supplies are independent connection brought out to pins.
Table 77. Power Supplies
FPGA Supplies VDD15 VDD33 VDD33_FPGAPLL VDDIO0 VDDIO1 VDDIO5 VDDIO6 VDDIO7
The ORSPI4 SPI4 embedded core requires an isolated 1.5V supply connected to four dedicated VDDA_SPI[A:D] pins. This supply is used to power the analog circuitry of the core between the LVDS I/O and the digital logic. The LVDS bus also requires connections to pins used for AC center-tap termination. The dedicated LVCTAP pins should be connected to GND through a 0.01 uFd capacitor. The QDR memory controller portion of the embedded core has dedicated HSTL I/O buffers which require an additional 1.5V supply known as VDDH. The HSTL input buffers uses an external reference voltage. The reference voltage connects to the REFI_[1:4] pins. The REFI pins should ideally be connected to a noise immune source that is exactly 1/2 the value of the VDDH supply.
Table 78. Embedded Core Power Supplies
Supply Description SERDES Input Buffers (1.5/1.8V) SERDES Guardband (1.5V) SERDES Output Buffers (1.5/1.8V) SERDES Analog (1.5V) SPI (1.5V) Memory Controller PLL (3.3V) HSTL Input Buffer Reference Voltage (VDDH/2) VDDA_SPIA VDDOB_A VDDIB_A VDDIB_B VDDGB VDDOB_B VDDA_SPIB VDDOB_C VDDA_SPIC VDDOB_D VDDA_SPID VDD_ANA VDDA_PLL REFI_1 REFI_2 REFI_3 REFI_4 HSTL Output Buffer Supply (1.5V) VDDH Name VDDIB_C VDDIB_D
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Lattice Semiconductor Recommended Power Supply Connections
Ideally, a board should have the power supplies described below: * VDD33, VDD33_FPGAPLL and VDDIO supplies for the FPGA Logic * A single 1.5 V source to supply power to FPGA and core digital logic. (VDD15)
ORCA ORSPI4 Data Sheet
* A dedicated 1.5 V power supply for the SERDES analog power pins. This will allow the end user to minimize noise. The guard band pins can also be sourced from the analog power supplies. (VDD_ANA, VDDGB) * SERDES TX output buffer power. The power supplies to the SERDES TX output buffers should be isolated from the rest of the board power supplies. Special care must be taken to minimize noise when providing board level power to these output buffers. The power supply can be 1.5 V or 1.8 V depending on the end application. (VDDOB) * SERDES RX input buffer power. The power supplies to the SERDES RX input buffers should be isolated from the rest of the board power supplies. Special care must be taken to minimize noise when providing board level power to these input buffers. The power supply can be 1.5 V or 1.8 V depending on the end application. (VDDIB) * An isolated 1.5V supply for the VDDA_SPI to minimize noise from the common 1.5V board supply. (VDD_SPI[A:D]) * The memory controller bus requires a dedicated 1.5V supply connected to the VDDH pins for HSTL output buffer supply voltage. (VDDH) * The HSTL input buffers of the Memory Controller require a voltage reference connected to the REFI pins which is half the VDDH supply. This supply should be filtered, and should not exceed a peak-to-peak AC noise of 2% of the VREF (DC). The HSTL buffer scheme also requires a termination resistor per signal. It is recommended that the clock pin termination be filtered separately from the data/control pin termination to minimize noise. * The VDDA_PLL supply pin requires a noise minimized 3.3V supply.
Recommended Power Supply Filtering Scheme
The board connections of the various SERDES VDD and VSS pins are critical to system performance. An example demonstration board schematic is available at www.latticesemi.com. Power supply filtering is in the form of: * A parallel bypass capacitor network consisting of 10 f, 0.1 f, and 1.0 f caps close to the power source. * A parallel bypass capacitor network consisting of 0.01 f and 0.1 f close to the pin. * The decoupling capacitor sizes are important as is the employment of various styles of capacitors. This provides frequency response coverage across a greater frequency bandwidth. General decoupling guidelines can be found in Lattice Semiconductor Application Note TN1068. * Example connections are shown in Figure 101. The naming convention for the power supply sources shown in the figure are as follows: - Supply_1.5 V - All digital, auxiliary power pins. - Supply_VDDIB - Input RX buffer power pins for SERDES. - Supply_VDDOB - Output TX buffer power pins for SERDES. - Supply_VDDANA - TX analog power pins, RX analog power pins, guard band power pins for SERDES. - Supply_VDD33, VDDA_PLL - FPGA and Embedded PLL power pins. - Supply VDDA_SPIA, VDDA_SPIB, VDDA_SPIC, VDDA_SPID - Analog core 1.5V SPI supplies. - Supply VDDH - HSTL output buffer power supply of the QDR Memory Controller. - Supply REFI_1, REFI_2, REFI_3, REFI_4 - Voltage reference for HSTL input buffer of the QDR Memory Controller should be one-half VDDH
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Figure 101. Power Supply Filtering
SOURCE SUPPLY_1.5 V
ORCA ORSPI4 Data Sheet
4.7 H
PIN VDD15
0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS SUPPLY_VDD Analog
4.7 H
VDD_ANA 0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS --1 EACH FOR VDDGB_[A,B] SUPPLY_VDDIB
4.7 H
VDDIB
0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS SUPPLY_VDDOB
4.7 H
VDDOB
0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS
4.7 H
SUPPLY_1.5 V
PIN VDDH
0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS
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Lattice Semiconductor
Power Supply Filtering (Continued)
SOURCE SUPPLY_1.5 V
ORCA ORSPI4 Data Sheet
4.7 H
PIN VDDA_SPI
0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS SUPPLY_3.3 V
4.7 H
VDDA_PLL 0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS
SUPPLY_3.3 V
4.7 H
VDD33_FPGAPLL
0.1 f
10 f
1 f
0.01 f
0.1 f
--1 NETWORK FOR EVERY 2 PINS 1 H VDDH 1K Precision REFI[1:4] 1K Precision 0.01 f 0.1 f
--1 NETWORK FOR REFI_1 REFI_2 REFI_3 REFI_4
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ORCA ORSPI4 Data Sheet
Pin Descriptions
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-programmable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor. If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor after configuration. The pin descriptions in Table and throughout this data sheet show active-low signals with an overscore. The package pinout tables that follow, show this as a signal ending with _N. For example LDC and LDC_N are equivalent.
Table 79. Pin Descriptions
Symbol Dedicated Pins VDD33 VDD33_FPGAPLL VDD15 VDDIO VSS PTEMP RESET -- 3.3V positive power supply. This power supply is used for 3.3 V configuration RAMs. -- 3.3V positive power supply. This power supply is used for 3.3 V internal PLLs. This power supply should be well isolated from all other power supplies on the board for proper operation. -- 1.5 V positive power supply for internal logic. -- Positive power supply used by I/O banks. -- Ground. I I Temperature sensing diode pin. Dedicated input. During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset. In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration data in. In the slave or readback after configuration, CCLK is input synchronous with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. As an input, a low level on DONE delays FPGA start-up after configuration.1 As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has an optional pull-up resistor.
PRGRM is an active-low input that forces the restart of configuration and resets the boundaryscan circuitry. This pin always has an active pull-up.
I/O
Description
CCLK
O I
DONE
I O
PRGRM RD_CFG
I I
This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0. RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary-scan, TDO is test data out. During JTAG, slave, master, and asynchronous peripheral configuration assertion on this CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low interrupt request output, when the MPI is used. Reference resistor connection for controlled impedance termination of Series 4 FPGA LVDS inputs. During power up and initialization, M0--M3 are used to select the configuration mode with their values latched on the rising edge of INIT. During configuration, a pull-up is enabled. Semi-dedicated PLL clock pins. During configuration they are 3-stated with a pull up. Pins dedicated for the primary clock. Input pins on the middle of each side with differential pairing.
RD_DATA/TDO CFG_IRQ/MPI_IRQ
O O
LVDS_R Special-Purpose Pins M[3:0]
-
I
I/O After configuration, these pins are user-programmable I/O.1 PLL_CK[0:7][TC] P[TBLR]CLK[1:0][TC] I I I/O These pins are user-programmable I/O pins if not used by PLLs after configuration.
I/O After configuration these pins are user programmable I/O, if not used for clock inputs.
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Table 79. Pin Descriptions (Continued)
Symbol TDI, TCK, TMS I/O I Description
ORCA ORSPI4 Data Sheet
If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If boundary-scan is not selected, all boundary-scan functions are inhibited once configuration is complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled during configuration. During configuration in asynchronous peripheral mode, RDY/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used. High During Configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete.
Low During Configuration is output low until configuration is complete. It is used as a control output, indicating that configuration is not complete.
I/O After configuration, these pins are user-programmable I/O if boundary scan is not used.1 RDY/BUSY/RCLK O
I/O After configuration this pin is a user-programmable I/O pin.1 HDC O
I/O After configuration, this pin is a user-programmable I/O pin.1 LDC O
I/O After configuration, this pin is a user-programmable I/O pin.1 INIT I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before the start of configuration. After configuration, this pin is a user-programmable I/O pin.1 I
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-up is enabled. RD is used in the asynchronous peripheral configuration mode. A low on RD changes D[7:3] into a status output. WR and RD should not be used simultaneously. If they are, the write strobe overrides. This pin is also used as the MPI data transfer strobe. As a status indication, a high indicates ready, and a low indicates busy.
CS0, CS1
I/O After configuration, if MPI is not used, these pins are user-programmable I/O pins.1 RD/MPI_STRB I
WR/MPI_RW
I
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the FPGA. In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write transfer to the FPGA. During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus master utilizing the least-significant bits of the PowerPC 32-bit address. MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high indicates that the current transfer is not a burst. MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word. During master parallel mode A[21:0] address the configuration EPROMs up to 4M bytes. In MPI mode this is driven low indicating the MPI received the data on the write cycle or returned data on a read cycle.
I/O After configuration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.1 PPC_A[14:31] MPI_BURST MPI_BDIP I I I
MPI_TSZ[0:1] A[21:0] MPI_ACK
I O O
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1
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Lattice Semiconductor
Table 79. Pin Descriptions (Continued)
Symbol MPI_CLK I/O I Description
ORCA ORSPI4 Data Sheet
This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a source of the clock for the Embedded System Bus. If MPI is used this will be the AMBA bus clock. A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal system bus for the current transaction. This pin requests the MPC860 to relinquish the bus and retry the cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1 MPI_TEA O
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1 MPI_RTRY D[0:31] O I/O If not used for MPI these pins are user-programmable I/O pins after configuration.1 I/O Selectable data bus width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write transaction and driven by MPI in a read transaction. I D[7:0] receive configuration data during master parallel, peripheral, and slave parallel configuration modes when WR is low and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. D[7:3] output internal status for asynchronous peripheral mode when RD is low.
O DP[0:3]
I/O After configuration, if MPI is not used, the pins are user-programmable I/O pins.1 I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2] for D[16:23], and DP[3] for D[24:31]. After configuration, if MPI is not used, the pins are user-programmable I/O pin.1 I During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a pull-up is enabled. During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave devices. Data out on DOUT changes on the rising edge of CCLK.
DIN
I/O After configuration, this pin is a user-programmable I/O pin.1 DOUT O
TESTCFG
1 I/O After configuration, DOUT is a user-programmable I/O pin. I During configuration this pin should be held high, to allow configuration to occur. A pull up is enabled during configuration.
I/O After configuration, TESTCFG is a user programmable I/O pin.1
1. The FPGA States of Operation section in the ORCA Series 4 FPGAs data sheet contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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Lattice Semiconductor ORSPI4 SPI4 External I/O Description
ORCA ORSPI4 Data Sheet
This section describes device I/O signals to/from the SPI4 interface. Table 80 and Table 81 lists the external signals that interface to the SPI4 block.
Table 80. SPI4 External Transmit Path Interface Signals
Pin Name (j = A or B) TSCLKj TSTATj[1:0] jTSCLKN jTSCLKP jTSTATN[1:0] jTSTATP[1:0] jTDATN[15:0] jTDATP[15:0] jTCTLN jTCTLP jTDCLKN jTDCLKP jTREFCLK Direction O = FPSC Output I = FPSC Input I I I I I I O O O O O O I
Description LVTTL transmit status clock input. LVTTL transmit status input LVDS (negative) transmit status clock input LVDS (positive) transmit status clock input LVDS (negative) transmit status data input LVDS (positive) transmit status data input LVDS (negative) transmit SPI4 data output LVDS (positive) transmit SPI4 data output LVDS (negative) transmit SPI4 control signal output LVDS (positive) transmit SPI4 control signal output LVDS (negative) transmit SPI4 clock reference. (100 - > 450 MHz) LVDS (positive) transmit SPI4 clock reference. (100 - >450 MHz) SPI4 clock reference input.
Table 81. SPI4 External Receive Path Interface Signals
Pin Name (j = A or B) RSCLKj RSTATj[1:0] jRSCLKN jRSCLKP] jRSTATN[1:0] jRSTATP[1:0 jRDATN[15:0] jRDATP[15:0] jRCTLN jRCTLP jRDCLKN jRDCLKP Direction O = FPSC Output I = FPSC Input O O O O O O I I I I I I
Description LVTTL receive status clock output. LVTTL receive status output LVDS (negative) receive status clock output LVDS (positive) receive status clock output LVDS (negative) receive status data output LVDS (positive) receive status data output LVDS (negative) receive SPI4 data input LVDS (positive) receive SPI4 data input LVDS (negative) receive SPI4 control signal input LVDS (positive) receive SPI4 control signal input LVDS (negative) receive SPI4 clock reference. (100 - >450 MHz) LVDS (positive) receive SPI4 clock reference. (100 - >450 MHz)
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Lattice Semiconductor
Table 82. SPI4 Miscellaneous System Signals
Pin Name (j = A or B) REF10 REF14 RESHI RESLO ALVCTAP1 ALVCTAP2 ALVCTAP3 ALVCTAP4 ALVCTAP5 BLVCTAP1 BLVCTAP2 BLVCTAP3 BLVCTAP4 BLVCTAP5 SPARE_1 SPARE_2 Direction O = FPSC Output I = FPSC Input I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
ORCA ORSPI4 Data Sheet
Description LVDS Reference voltage: 1.0 V +/- 3% LVDS Reference voltage: 1.4 V +/- 3% LVDS resistor high pin (100 . in series with RESLO) LVDS resistor low pin (100 . in series with RESHI) LVDS input center tap (use 0.01 F to GND) LVDS input center tap (use 0.01 F to GND) LVDS input center tap (use 0.01 F to GND) LVDS input center tap (use 0.01 F to GND) LVDS input center tap (use 0.01 F to GND) LVDS input center tap (use 0.01 F to GND) LVDS input center tap (use 0.01 F to GND) LVDS input center tap (use 0.01 F to GND) LVDS input center tap (use 0.01 F to GND) LVDS input center tap (use 0.01 F to GND) Reserved Reserved
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Lattice Semiconductor ORSPI4 SERDES External I/O Description
ORCA ORSPI4 Data Sheet
This section describes device I/O signals to/from the SERDES. Table 83 lists the external signals that interface to the SERDES block.
Table 83. SERDES External Interface Signals
Direction O = FPSC Output I = FPSC Input
Pin Name SERDES Interface Pins HDINP_A HDINN_A HDINP_B HDINN_B HDINP_C HDINN_C HDINP_D HDINN_D HDOUTP_A HDOUTN_A HDOUTP_B HDOUTN_B HDOUTP_C HDOUTN_C HDOUTP_D HDOUTN_D REFCLKP REFCLKN REXT REXTN
Description
I I I I O O O O I ---
Serial Input for channel A Serial Input for channel B Serial Input for channel C Serial Input for channel D Serial Output for channel A Serial Output for channel B Serial Output for channel C Serial Output for channel D Reference clock to SERDES quad Reference resistor Reference resistor. A 3.32 KW 1% resistor must be connected across REXT and REXTN. This current should handle a total of 300A. Global Reset Integrated 50K pull-down allows chip to stay in reset state when external driver loses power LVTTL test mode pins with integrated 50K pull-ups that default chip into operational mode when un-driven. Power-down active low. Puts Core into low-power (non-functional) state. Active low control input causes all output pins to be disabled. (See Note 1) Chip test pin. Integrated 50K pull-up
Misc System Signals RESETN I TESTMD[1:0]N PDN TRISTN TESTCLK I I I I
1. Should be externally connected on board to 3.3 V pullup resistor.
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Lattice Semiconductor ORSPI4 Memory Controller External I/O Description
ORCA ORSPI4 Data Sheet
This section describes device I/O signals to/from the Memory Controller. Table 84 lists the external signals that interface to the Memory Controller block.
Table 84. Memory Controller External Interface Signals
QDRII SDRAM Pin Name K,K# D(35:0) SA(17:0) W# R# CQ,CQ# Q(35:0) Direction O = FPSC Output I = FPSC Input O O O O O I I I I I
Pin Name PMIK, PMIKN PMID(35:0) PMIA(17:0) PMIWN PMIRN PMIC, PMICN PMIQ(35:0) REFCLK Source Inputs MCREFCLK ATREFCLK BTREFCLK Other Signals EXT_1K
Description Clock for write data D, address SA, and enables W# and R# Write data bus Address bus Write enable (active-LO) Read enable (active-LO) Clock for read data Q Read data bus Dedicated Memory Controller reference clock (HSTL) SPIA reference clock (LVTTL). Note that this signal also is fed to the SPIA block. SPIB reference clock, (LVTTL). Note that this signal also is fed to the SPIB block. Reference resistor. Connect to a 1.5 K 1% precision resistor to ground. This current should handle a total of 700 A.
Interface to QDRII SDRAM
-
-
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Lattice Semiconductor Package I/O
Table 85. I/O Summary
ORCA ORSPI4 Data Sheet
Package I/O Type User programmable I/O Available programmable differential pair pins FPGA configuration pins FPGA dedicated function pins Core function pins VDD15 VDD33 VDD33_FPGAPLL VDDIO VSS VDDGB VDDIB VDDOB VDD_ANA VDDA_SPI[A:D] VDDA_PLL VDDH HSTL VREF No connect Total package pins FTE1036 498 498 7 2 322 42 14 8 30 79 1 4 8 4 4 1 8 4 0 1036 F1156/FN1156 356 356 7 2 301 80 30 8 50 187 0 0 0 0 4 1 30 4 96 1156
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Lattice Semiconductor Pin Tables
ORCA ORSPI4 Data Sheet
The ORSPI4 FPSC is available in two package types; a 1156-pin fpBGA package, and a 1036-pin ftSBGA package. Both packages are 1.0 mm pitch packages. The 1036-pin package offers two SPI4 interfaces, or one SPI4 interface and a quad 0.6-3.7 Gbps SERDES, a highspeed QDR-II SRAM Memory Controller, and 498 user I/Os on the FPGA array. The 1156-pin package offers two SPI4 interfaces (no SERDES available on this package offering), a high-speed QDR-II SRAM Memory Controller, and 356 user I/Os on the FPGA array.
Table 86. 1156 fpBGA Pin Table
F1156 VDDIO Ball Bank F4 G4 H4 J4 H5 H6 J6 J5 H3 J3 K4 K5 G2 G1 L5 L4 H2 H1 J2 J1 K2 K1 K3 L3 L2 L1 M4 M5 N5 N4 M3 N3 P4 VREF Group O I I I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PRD_DATA PRESET_N PRD_CFG_N PPRGRM_N PL2D PL2C PL3D PL3C PL4D PL4C PL5D PL5C PL6D PL6C PL7D PL7C PL8D PL8C PL9D PL9C PL10D PL10C PL11D PL11C PL12D PL12C PL13D PL13C PL14D PL14C PL15D PL15C PL16D Additional Function RD_DATA/TDO RESET_N RD_CFG_N PRGRM_N PLL_CK0C/HPPLL PLL_CK0T/HPPLL VREF_0_07 D5 D6 VREF_0_08 HDC LDC_N TESTCFG D7 VREF_0_09 A17/PPC_A31 CS0_N CS1 INIT_N DOUT VREF_0_10 A16/PPC_A30 A15/PPC_A29 A14/PPC_A28 VREF_7_01 L1C L1T L2C L2T L3C L3T L4C L4T L5C L5T L6C L6T L7C L7T L8C L8T L9C L9T L10C L10T L11C L11T L12C L12T L13C L13T L14C L14T L15C F1156 Pair
0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1
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Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank P3 M2 M1 N2 N1 P5 R5 R4 R3 P2 P1 T3 T4 R1 R2 R6 T6 T5 U5 U3 U4 T1 T2 V3 V4 U1 U2 V5 W5 W3 W4 V1 V2 W1 W2 Y1 Y2 AA1 AA2 Y3 W6 AA3 7 (CL) 1 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 4 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PL16C PL17D PL17C PL18D PL18C PL19D PL19C PL20D PL20C PL21D PL21C PL22D PL22C PL23D PL23C PL24D PL24B PL24C PL24A PL25D PL25C PL26D PL26C PL27D PL27C PL28D PL28C PL29D PL29C PL30D PL30C PL31D PL31C PL32D PL32C PL33D PL33C PL34D PL34C PL35D PL35B PL35C D4 -
ORCA ORSPI4 Data Sheet
Additional Function
F1156 Pair L15T L16C L16T L17T L18C L18T L19C L19T L20C L20T L21C L21T L22C L22T L23C L178C L23T L178T L24C L24T L25C L25T L26C L26T L27C L27T L28C L28T L29C L29T L30C L30T L31C L31T L32C L32T L33C L33T L34C L35C L34T
RDY/BUSY_N/RCLK L17C VREF_7_02 A13/PPC_A27 A12/PPC_A26 A11/PPC_A25 VREF_7_03 RD_N/MPI_STRB_ N VREF_7_04 PLCK0C PLCK0T A10/PPC_A24 A9/PPC_A23 A8/PPC_A22 VREF_7_05 PLCK1C PLCK1T VREF_7_06 A7/PPC_A21 A6/PPC_A20 A5/PPC_A19 WR_N/MPI_RW VREF_7_07 A4/PPC_A18 VREF_7_08 A3/PPC_A17 A2/PPC_A16
7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8
206
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank Y6 AB1 Y5 AB2 Y4 AC1 AA5 AC2 AA4 AD1 AA6 AD2 AB6 AB3 AB4 AC3 AB5 AE1 AC4 AE2 AC5 AF1 AD5 AF2 AD4 AD3 AE4 AE3 AE5 AG1 AF4 AG2 AF5 AH1 AC6 AH2 AD6 AF3 AE6 AG3 AF6 AJ1 AJ2 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 4 6 (BL) 3 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PL35A PL36D PL36B PL36C PL36A PL37D PL37B PL37C PL37A PL38D PL38B PL38C PL38A PL39D PL39B PL39C PL39A PL40D PL40B PL40C PL40A PL41D PL41B PL41C PL41A PL42D PL42B PL42C PL42A PL43D PL43B PL43C PL43A PL44D PL44B PL44C PL44A PL45D PL45B PL45C PL45A PL46D PL46C -
ORCA ORSPI4 Data Sheet
Additional Function A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 D9 D10 VREF_6_02 D11 D12 VREF_6_03 D13 VREF_6_04 -
F1156 Pair L35T L36C L37C L36T L37T L38C L39C L38T L39T L40C L41C L40T L41T L42C L43C L42T L43T L44C L45C L44T L45T L46C L47C L46T L47T L48C L49C L48T L49T L50C L51C L50T L51T L52C L53C L52T L53T L54C L55C L54T L55T L56C L56T
207
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AH3 AJ3 AG4 AH4 AH6 AN5 AH7 AP5 AN6 AP6 AK6 AK7 AJ6 AL6 AJ7 AL7 AG7 AM6 AG8 AM7 AG9 AN7 AG10 AP7 AH8 AN8 AJ8 AP8 AH9 AK8 AJ9 AK9 AJ10 AL8 AH10 AL9 AM8 AM9 AJ11 AN9 AH11 AP9 AG11 6 (BL) 4 6 (BL) 4 VREF Group IO IO I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PL47D PL47C PTEMP LVDS_R PB2A PB2C PB2B PB2D PB3C PB3D PB4C PB4D PB5A PB5C PB5B PB5D PB6A PB6C PB6B PB6D PB7A PB7C PB7B PB7D PB8A PB8C PB8B PB8D PB9A PB9C PB9B PB9D PB10A PB10C PB10B PB10D PB11C PB11D PB12A PB12C PB12B PB12D PB13A
ORCA ORSPI4 Data Sheet
Additional Function PLL_CK7C/HPPLL PLL_CK7T/HPPLL PTEMP LVDS_R DP2 PLL_CK6T/PPLL PLL_CK6C/PPLL VREF_6_05 DP3 VREF_6_06 D14 D15 D16 D17 D18 VREF_6_07 D19 D20 D21 VREF_6_08 D22 -
F1156 Pair L57C L57T L58T L59T L58C L59C L60T L60C L61T L61C L62T L63T L62C L63C L64T L65T L64C L65C L66T L67T L66C L67C L68T L69T L68C L69C L70T L71T L70C L71C L72T L73T L72C L73C L74T L74C L75T L76T L75C L76C L77T
6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 9
208
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AK10 AG12 AK11 AJ12 AN10 AH12 AP10 AJ13 AL10 AH13 AL11 AJ14 AM10 AH14 AM11 AJ16 AN11 AH16 AP11 AJ17 AK12 AH17 AK13 AG13 AN12 AG14 AP12 AH15 AL12 AJ15 AL13 AJ18 AM12 AH18 AM13 AJ19 AN13 AH19 AP13 AP14 AN14 AG15 AK14 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PB13C PB13B PB13D PB14A PB14C PB14B PB14D PB15A PB15C PB15B PB15D PB16A PB16C PB16B PB16D PB17A PB17C PB17B PB17D PB18A PB18C PB18B PB18D PB19A PB19C PB19B PB19D PB20A PB20C PB20B PB20D PB21A PB21C PB21B PB21D PB22A PB22C PB22B PB22D PB23C PB23D PB24A PB24C D23 D24 -
ORCA ORSPI4 Data Sheet
Additional Function
F1156 Pair L78T L77C L78C L79T L80T L79C L80C L81T L82T L81C L82C L83T L84T L83C L84C L85T L86T L85C L86C L87T L88T L87C L88C L89T L90T L89C L90C L91T L92T L91C L92C L93T L94T L93C L94C L95T L96T L95C L96C L97T L97C L99T L98T
VREF_6_09 D25 D26 D27 VREF_6_10 D28 D29 D30 VREF_6_11 D31 VREF_5_01 PBCK0T PBCK0C VREF_5_02
209
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AG16 AK15 AL14 AL15 AM14 AM15 AG18 AN15 AG17 AP15 AL16 AM16 AN16 AP16 AK16 AK17 AN17 AP17 AL17 AM17 AK18 AL18 AN18 AP18 AN19 AP19 AM18 AM19 AN20 AP20 AL19 AL20 AK19 AK20 AM20 AM21 AN21 AP21 AN22 AP22 AL21 AL22 AK21 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 6 5 (BC) 6 5 (BC) 6 5 (BC) 6 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 9 5 (BC) 9 5 (BC) 9 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PB24B PB24D PB25C PB25D PB26C PB26D PB27A PB27C PB27B PB27D PB28C PB28D PB29C PB29D PB30C PB30D PB31C PB31D PB32C PB32D PB33C PB33D PB34C PB34D PB35C PB35D PB36C PB36D PB37C PB37D PB38C PB38D PB39C PB39D PB40C PB40D PB41C PB41D PB42C PB42D PB43C PB43D PB44C -
ORCA ORSPI4 Data Sheet
Additional Function
F1156 Pair L99C L98C L100T L100C L101T L101C L102T L103T L102C L103C L104T L104C L105T L105C L106T L106C L107T L107C L108T L108C L109T L109C L110T L110C L111T L111C L112T L112C L113T L113C L114T L114C L115T L115C L116T L116C L117T L117C L118T L118C L119T L119C L120T
VREF_5_03 PBCK1T PBCK1C VREF_5_04 VREF_5_05 VREF_5_06 VREF_5_07 VREF_5_08 -
210
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AK22 AM22 AM23 AN23 AP23 AL23 AK23 AP24 AN24 AM24 AL24 AK24 AP25 AN25 AG22 AM25 AH23 AL25 AH24 AK30 AL31 AJ30 AK31 AM31 AE27 AL32 AF29 AH30 AG28 AM32 AF28 AM33 AE28 AK32 AL33 AJ32 AL34 AJ31 AE26 AH31 AD26 AK33 AJ33 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 10 5 (BC) 10 VREF Group IO IO IO IO IO I I I I I I I I I I I O O O I I I I I I/O I I I/O I I I I I O O O O O O O O O O I/O Pin Description PB44D PB45C PB45D PB46C PB46D RESETN TRISTN TESTMD1N TESTMD0N PDN ATREFCLK TESTCLK BTREFCLK TSTAT1B TSTAT0B TSCLKB RSTAT1B RSTAT0B RSCLKB ATSTAT1N ATSTAT0N ATSTAT1P ATSTAT0P ATSCLKN ALVCTAP5 ATSCLKP BTSCLKN BLVCTAP5 BTSCLKP BTSTAT1N BTSTAT0N BTSTAT1P BTSTAT0P BRSTAT1N BRSTAT0N BRSTAT1P BRSTAT0P BRSCLKN ARSCLKN BRSCLKP ARSCLKP ARSTAT1N ARSTAT0N -
ORCA ORSPI4 Data Sheet
Additional Function VREF_5_09
F1156 Pair L120C L121T L121C L122T L122C R1C R2C R1T R2T R3C R3T R4C R4T R5C R6C R5T R6T R7C R8C R7T R8T R9C R10C R9T R10T R11C R12C
VREF_5_10 -
211
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AK34 AJ34 AF31 AD28 AG31 AE29 AH32 AG29 AG32 AG30 AH33 AD27 AH34 AC27 AG33 AE30 AG34 AF30 AF32 AD30 AE32 AD29 AF33 AB26 AF34 AC26 AE31 AD31 AC28 AE33 AC29 AE34 AD32 AB28 AC32 AB29 AD33 AC30 AD34 AB30 AC31 AB27 AB31 VREF Group O O I I I I O O O O O O O O O O O O O O O O O O O O VDDA_SPIA VSS O O O O O O O O O O O O O O O I/O Pin Description ARSTAT1P ARSTAT0P RESLO RESHI REF14 REF10 BTDAT15N BTDAT14N BTDAT15P BTDAT14P BTDAT13N BTDAT12N BTDAT13P BTDAT12P BTDAT11N BTDAT10N BTDAT11P BTDAT10P BTDAT9N BTDAT8N BTDAT9P BTDAT8P BTCTLN BTDCLKN BTCTLP BTDCLKP VDDA_SPIA VSS BTDAT7N BTDAT6N BTDAT7P BTDAT6P BTDAT5N BTDAT4N BTDAT5P BTDAT4P BTDAT3N BTDAT2N BTDAT3P BTDAT2P BTDAT1N BTDAT0N BTDAT1P -
ORCA ORSPI4 Data Sheet
Additional Function
F1156 Pair R11T R12T R13C R14C R13T R14T R15C R16C R15T R16T R17C R18C R17T R18T R19C R20C R19T R20T R21C R22C R21T R22T R23C R24C R23T R24T R25C R26C R25T R26T R27C R28C R27T R28T R29C R30C R29T
212
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AA27 AC33 AA29 AC34 AA30 AA31 AA26 AB33 Y26 AB34 AA28 AB32 Y28 AA32 Y30 AA33 Y29 Y31 Y27 Y32 W27 AA34 W28 Y34 W30 Y33 W29 W33 W26 W31 V26 W32 V28 W34 V30 V34 V29 V33 V27 V32 U27 V31 U31 VREF Group O I I I I I/O I I I I I I I I I I/O I I I I I I I/O I I I I I I I I I I/O I I I I I I I I VSS VDDA_SPIB I/O Pin Description BTDAT0P BRDCLKN BRDAT15N BRDCLKP BRDAT15P BLVCTAP1 BRDAT14N BRDAT13N BRDAT14P BRDAT13P BRDAT12N BRDAT11N BRDAT12P BRDAT11P BRDAT10N BLVCTAP2 BRDAT10P BRDAT9N BRDAT8N BRDAT9P BRDAT8P BRCTLN BLVCTAP3 BRCTLP BRDAT7N BRDAT6N BRDAT7P BRDAT6P BRDAT5N BRDAT4N BRDAT5P BRDAT4P BLVCTAP4 BRDAT3N BRDAT2N BRDAT3P BRDAT2P BRDAT1N BRDAT0N BRDAT1P BRDAT0P VSS VDDA_SPIB -
ORCA ORSPI4 Data Sheet
Additional Function
F1156 Pair R31T R32C R33C R32T R33T R34C R35C R34T R35T R36C R37C R36T R37T R38C R38T R39C R40C R39T R40T R41C R41T R42C R43C R42T R43T R44C R45C R44T R45T R46C R47C R46T R47T R48C R49C R48T R49T -
213
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank U28 U32 U29 U33 U34 U30 T34 T29 T33 T32 U26 T31 T26 R34 T28 R33 T30 R32 T27 R31 R27 P34 R28 P33 R29 N34 R30 N33 P30 P32 R26 P31 P26 M34 P28 M33 P29 N31 M32 N32 L34 P27 L33 VREF Group O VSS O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O VSS VDDA_SPIC VSS I I I I/O Pin Description ATDAT15N VSS ATDAT15P ATDAT14N ATDAT14P ATDAT13N ATDAT12N ATDAT13P ATDAT12P ATDAT11N ATDAT10N ATDAT11P ATDAT10P ATDAT9N ATDAT8N ATDAT9P ATDAT8P ATCTLN ATDCLKN ATCTLP ATDCLKP ATDAT7N ATDAT6N ATDAT7P ATDAT6P ATDAT5N ATDAT4N ATDAT5P ATDAT4P ATDAT3N ATDAT2N ATDAT3P ATDAT2P ATDAT1N ATDAT0N ATDAT1P ATDAT0P VSS VDDA_SPIC VSS ARDCLKN ARDAT15N ARDCLKP -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair R50C R50T R51C R51T R52C R53C R52T R53T R54C R55C R54T R55T R56C R57C R56T R57T R58C R59C R58T R59T R60C R61C R60T R61T R62C R63C R62T R63T R64C R65C R64T R65T R66C R67C R66T R67T R68C R69C R68T
214
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank N27 L32 N30 K34 M30 K33 N28 J32 N29 K32 L30 M31 N26 L31 M26 J34 M28 J33 M29 K31 L27 H34 M27 H33 L29 J31 K30 H31 L28 G34 J30 G33 H30 F34 L26 F33 K26 H32 G32 G30 G31 H29 F32 VREF Group I I/O I I I I I I I I I/O I I I I I I I I I/O I I I I I I I I I/O I I I I I I I I VDDA_SPID VSS I I I O I/O Pin Description ARDAT15P ALVCTAP1 ARDAT14N ARDAT13N ARDAT14P ARDAT13P ARDAT12N ARDAT11N ARDAT12P ARDAT11P ALVCTAP2 ARDAT10N ARDAT9N ARDAT10P ARDAT9P ARDAT8N ARCTLN ARDAT8P ARCTLP ALVCTAP3 ARDAT7N ARDAT6N ARDAT7P ARDAT6P ARDAT5N ARDAT4N ARDAT5P ARDAT4P ALVCTAP4 ARDAT3N ARDAT2N ARDAT3P ARDAT2P ARDAT1N ARDAT0N ARDAT1P ARDAT0P VDDA_SPID VSS TSTAT1A TSTAT0A TSCLKA RSTAT1A -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair R69T R70C R71C R70T R71T R72C R73C R72T R73T R74C R75C R74T R75T R76C R77C R76T R77T R78C R79C R78T R79T R80C R81C R80T R81T R82C R83C R82T R83T R84C R85C R84T R85T -
215
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank K29 E34 E33 D34 K28 D33 G29 C33 K27 E32 D32 C32 G28 B32 J29 C31 J28 D31 J27 F30 H27 E31 H28 F31 F29 E30 F28 D30 E27 C30 F27 B31 G27 A31 E26 B30 F26 A30 G26 E29 H26 E28 E25 VREF Group O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Description RSTAT0A RSCLKA PMIA17 PMIA16 PMIA15 PMIA14 PMIA13 PMIA12 PMIA11 PMIA10 PMIA9 PMIA8 PMIWN PMIRN PMIA7 REFI_1 PMIA6 PMIA5 PMIA4 PMIA3 PMIA2 PMIA1 PMIA0 EXT_1K PMID35 PMID34 PMID33 PMID32 PMID31 PMID30 PMID29 PMID28 PMID27 PMID26 PMID25 PMID24 PMID23 PMID22 PMID21 PMID20 PMID19 PMID18 PMID17 -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
216
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank D29 C29 F25 B29 G25 A29 H25 D28 E24 C28 F24 B28 G24 A28 H24 D27 E23 C27 F23 B27 A27 G23 D26 H23 C26 E22 B26 F22 A26 E21 D25 G22 C25 F21 B25 G20 A25 F20 D24 E20 C24 G21 B24 VREF Group I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Description PMID16 REFI_2 PMIK PMIKN PMID15 PMID14 PMID13 PMID12 PMID11 PMID10 PMID9 PMID8 PMID7 PMID6 PMID5 PMID4 PMID3 PMID2 PMID1 PMID0 REFI_3 PMIC PMICN PMIQ35 PMIQ34 PMIQ33 PMIQ32 PMIQ31 PMIQ30 PMIQ29 PMIQ28 PMIQ27 PMIQ26 PMIQ25 PMIQ24 PMIQ23 PMIQ22 PMIQ21 PMIQ20 PMIQ19 PMIQ18 PMIQ17 PMIQ16 -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
217
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank H22 A24 E19 D23 F19 C23 G19 B23 H21 A23 H20 D22 H19 C22 H18 B22 E18 A22 F18 C21 G18 B21 A21 A20 A19 C20 B20 B19 A18 C19 D19 B18 A17 C18 D18 B17 C17 A16 B16 A15 B15 A14 B14 VREF Group I/O I/O I/O VREF I/O I/O I/O VDDA_PLL I/O VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description MCREFCLK SPARE_2 PMIQ15 REFI_4 PMIQ14 PMIQ13 PMIQ12 VDDA_PLL PMIQ11 VSS PMIQ10 PMIQ9 PMIQ8 PMIQ7 PMIQ6 PMIQ5 PMIQ4 PMIQ3 PMIQ2 PMIQ1 PMIQ0 PT46D PT46C PT45D PT45C PT44D PT44C PT43D PT43C PT42D PT42C PT41D PT41C PT40D PT40C PT39D PT39C PT38D PT38C PT37D PT37C PT36D PT36C -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10
L123C L123T L124C L124T L125C L125T L126C L126T L127C L127T L128C L128T L129C L129T L130C L130T L131C L131T L132C L132T L133C L133T
VREF_1_07 VREF_1_08 VREF_1_09 VREF_1_10 -
218
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank E17 H17 E16 G17 C16 G15 C15 F15 D17 F14 D16 G14 F17 H16 F16 G16 A13 F13 B13 F12 C14 G13 C13 H13 D15 G12 D14 H12 A12 H15 B12 H14 D13 D12 E15 E14 A11 J14 A10 J13 C12 C11 B11 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 5 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PT35D PT35B PT35C PT35A PT34D PT34B PT34C PT34A PT33D PT33B PT33C PT33A PT32D PT32B PT32C PT32A PT31D PT31B PT31C PT31A PT30D PT30B PT30C PT30A PT29D PT29B PT29C PT29A PT28D PT28B PT28C PT28A PT27D PT27C PT26D PT26C PT25D PT25B PT25C PT25A PT24D PT24C PT23D -
ORCA ORSPI4 Data Sheet
Additional Function
F1156 Pair L134C L135C L134T L135T L136C L137C L136T L137T L138C L139C L138T L139T L140C L141C L140T L141T L142C L143C L142T L143T L144C L145C L144T L145T L146C L147C L146T L147T L148C L149C L148T L149T L150C L150T L151C L151T L152C L153C L152T L153T L154C L154T L155C
VREF_1_01 VREF_1_02 VREF_1_03 VREF_1_04 PTCK1C
219
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank B10 E13 E12 A9 B9 C10 C9 D11 D10 A8 B8 H11 G11 H10 G10 A7 B7 C8 C7 E11 E10 F11 F10 D9 D8 H9 G9 H7 G7 A6 B6 E9 E8 F9 F8 C6 C5 D7 D6 E7 G8 E6 H8 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 6 0 (TL) 6 0 (TL) 6 0 (TL) 6 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PT23C PT22D PT22C PT21D PT21C PT20D PT20C PT19D PT19C PT18D PT18C PT17D PT17C PT16D PT16C PT15D PT15C PT14D PT14C PT13D PT13C PT12D PT12C PT11D PT11C PT10D PT10C PT9D PT9C PT8D PT8C PT7D PT7C PT6D PT6C PT5D PT5C PT4D PT4C PT3D PT3B PT3C PT3A
ORCA ORSPI4 Data Sheet
Additional Function PTCK1T PTCK0C PTCK0T VREF_1_05 VREF_1_06 MPI_RTRY_N MPI_ACK_N VREF_0_01 M0 M1 MPI_CLK M2 M3 VREF_0_02 MPI_TEA_N VREF_0_03 D0 TMS A20/MPI_BDIP_N A19/MPI_TSZ1 A18/MPI_TSZ0 D3 VREF_0_04 D1 D2 VREF_0_05 TDI TCK VREF_0_06 -
F1156 Pair L155T L156C L156T L157C L157T L158C L158T L159C L159T L160C L160T L161C L161T L162C L162T L163C L164C L164T L165C L165T L166C L166T L167C L167T L168C L168T L169C L169T L170C L170T L171C L171T L172C L172T L173C L173T L174C L174T L175C L176C L175T L176T
A21/MPI_BURST_N L163T
220
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank F7 F6 G5 G6 F5 AA24 AA8 AA9 AB8 AB9 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC23 AC8 AC9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD8 AE10 AE11 AE12 AE13 AE14 AE15 AE16 0 (TL) 6 0 (TL) 6 VREF Group IO IO O IO IO VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 I/O Pin Description PT2D PT2C PCFG_MPI_IRQ PCCLK PDONE VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15
ORCA ORSPI4 Data Sheet
Additional Function PLL_CK1C/PPLL PLL_CK1T/PPLL CFG_IRQ_N/MPI_I RQ_N CCLK DONE -
F1156 Pair L177C L177T -
221
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE9 K10 K11 K12 K9 L10 L11 L12 L13 L14 L15 L16 L8 M13 M14 M8 M9 N8 N9 P8 P9 R8 R9 T8 T9 U8 U9 V24 V8 V9 W24 W8 W9 Y24 Y8 Y9 VREF Group VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 I/O Pin Description VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
222
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE24 AE25 AF22 AF23 AF24 AF25 AG23 AG24 AG25 AH22 N24 N25 P24 P25 R24 R25 T24 T25 U24 U25 V25 W25 Y25 J7 K8 AE8 AF7 AH20 AH21 D20 D21 J19 J20 J21 J23 J25 VREF Group VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDDH VDDH VDDH VDDH VDDH I/O Pin Description VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDD33_FPGAPLL VDDH VDDH VDDH VDDH VDDH -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
223
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank K19 K20 K21 K23 K25 L18 L19 L20 L21 L23 M18 M19 M20 M21 M23 M25 N18 N19 N20 N21 N23 P18 P19 P20 P21 J10 J11 J12 J8 J9 K7 L7 M7 N7 P7 J15 J16 J17 J18 K13 K14 K15 K16 VREF Group VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 I/O Pin Description VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -
224
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank K17 K18 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AG19 AG20 AG21 AC7 AD7 AE7 AF10 AF11 AF12 AF13 AF14 AF8 AF9 AA7 AB7 R7 T7 U6 U7 V6 V7 W7 Y7 B5 D5 C34 D4 D3 D2 E5 E4 E3 E2 E1 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) VREF Group VDDIO1 VDDIO1 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 NC NC NC NC NC NC NC NC NC NC NC I/O Pin Description VDDIO1 VDDIO1 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO5 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
225
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank F3 B4 F2 F1 G3 P6 N6 M6 A5 L6 K6 AL5 AL4 AL3 AL2 AL1 AK5 AK4 AK3 A4 AK2 AK1 AM5 AM4 AM3 AM2 AN4 AN3 AP4 AJ5 B3 AJ4 AH5 AG5 AG6 AJ20 AJ25 AJ24 AJ23 AJ22 AJ21 C4 AJ29 VREF Group NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC I/O Pin Description -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
226
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AJ28 AJ27 AJ26 AH27 AH26 AG27 AG26 AF27 AF26 C3 AH25 AH29 AH28 AK29 AK28 AK27 AK26 AK25 AP29 AP28 C2 AP27 AP26 AN29 AN28 AN27 AN26 AM29 AM28 AM27 AM26 D1 AL29 AL28 AL27 AL26 A32 A33 A34 AL30 B34 B33 A1 VREF Group NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS VSS I/O Pin Description -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
227
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank A2 A3 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC10 AC11 AC12 AC20 AC21 AC22 AD9 AM1 AM30 AM34 AN1 AN2 AN30 VREF Group VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
228
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank AN31 AN32 AN33 AN34 AP1 AP2 AP3 AP30 AP31 AP32 AP33 AP34 B1 B2 C1 L17 L9 M10 M11 M12 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 P17 R10 R11 R12 R13 VREF Group VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
229
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank R14 R15 R16 R17 T10 T11 T12 T13 T14 T15 T16 T17 U10 U11 U12 U13 U14 U15 U16 U17 U18 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 W10 W11 W12 W13 W14 W15 W16 W17 VREF Group VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
230
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank W18 W19 W20 W21 W22 W23 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 J22 J24 J26 K22 K24 L22 L24 L25 M22 M24 N22 P22 P23 R18 R19 R20 R21 R22 R23 T18 T19 T20 T21 VREF Group VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
231
Lattice Semiconductor
Table 86. 1156 fpBGA Pin Table (Continued)
F1156 VDDIO Ball Bank T22 T23 U19 U20 U21 U22 U23 VREF Group VSS VSS VSS VSS VSS VSS VSS I/O Pin Description VSS VSS VSS VSS VSS VSS VSS -
ORCA ORSPI4 Data Sheet
Additional Function -
F1156 Pair
Note: All differential pairs use adjacent balls.
232
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Table 87. 1036 ftSBGA Pin Table
FTE1036 VDDIO Ball Bank J44 K42 J43 K43 K44 M42 M41 M40 L38 A1 M39 L39 N42 G30 N41 N40 L40 A2 N39 L41 P44 C42 P43 P42 L42 G31 P41 L43 R44 A11 R43 R42 M43 D42 R41 M44 T44 G36 T43 T42 N44 A22 VREF Group VDD33 O I I I IO IO IO IO VSS IO IO IO VDDIO0 IO IO IO VSS IO IO IO VDD15 IO IO IO VDDIO0 IO IO IO VSS IO IO IO VDD15 IO IO IO VDDIO0 IO IO IO VSS I/O Pin Description VDD33_FPGAPLL PRD_DATA PRESET_N PRD_CFG_N PPRGRM_N PL2D PL2C PL3D PL3B VSS PL3C PL3A PL4D VDDIO0 PL4C PL5D PL5B VSS PL5C PL5A PL6D VDD15 PL6C PL7D PL7B VDDIO0 PL7C PL7A PL8D VSS PL8C PL9D PL9B VDD15 PL9C PL9A PL10D VDDIO0 PL10C PL11D PL11B VSS RD_DATA/TDO RESET_N RD_CFG_N PRGRM_N PLL_CK0C/HPPLL PLL_CK0T/HPPLL VREF_0_07 D5 D6 VREF_0_08 HDC LDC_N TESTCFG D7 VREF_0_09 A17/PPC_A31 CS0_N CS1 Additional Function L1C L1T L3C L4C L3T L4T L5C L5T L7C L8C L7T L8T L9C L9T L11C L12C L11T L12T L13C L13T L15C L16C L15T L16T L17C L17T L19C L20C FTE1036 Pair
0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 7 0 (TL) 0 (TL) 7 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 8 0 (TL) 0 (TL) 8 0 (TL) 8 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 9 0 (TL) 0 (TL) 9 0 (TL) 10 0 (TL) 10 -
233
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank T41 N43 U44 E40 U43 U42 P40 U41 P39 V44 B2 V43 G34 V42 R40 G35 V41 R39 W44 T40 W38 W43 T39 W42 U40 B43 W41 U39 Y44 V40 G37 Y43 V39 Y42 W40 Y38 Y41 W39 AA44 Y40 B44 AA43 Y39 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 0 (TL) 10 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 1 7 (CL) 7 (CL) 1 7 (CL) 1 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 2 7 (CL) 7 (CL) 2 7 (CL) 2 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 VREF Group IO IO IO VDD15 IO IO IO IO IO IO VSS IO VSS IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO I/O Pin Description PL11C PL11A PL12D VDD15 PL12C PL13D PL13B PL13C PL13A PL14D VSS PL14C VSS PL15D PL15B VDD15 PL15C PL15A PL16D PL16B VDDIO7 PL16C PL16A PL17D PL17B VSS PL17C PL17A PL18D PL18B VDD15 PL18C PL18A PL19D PL19B VDDIO7 PL19C PL19A PL20D PL20B VSS PL20C PL20A -
ORCA ORSPI4 Data Sheet
Additional Function
FTE1036 Pair L19T L20T L21C L21T L23C L24C L23T L24T L25C L25T L27C L28C L27T L28T L29C L30C L29T L30T L31C L32C L31T L32T L34C L33T L34T L35C L36C L35T L36T L37C L38C L37T L38T
INIT_N DOUT VREF_0_10 A16/PPC_A30 A15/PPC_A29 A14/PPC_A28 VREF_7_01 D4 VREF_7_02 A13/PPC_A27 A12/PPC_A26 -
RDY/BUSY_N/RCLK L33C
234
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AA42 AA40 H38 AA41 AA39 AB44 AB40 AB38 AB43 AB39 AB42 AC40 G20 AB41 AC39 AC44 AD40 AC43 AD39 AC42 AE40 AC38 AC41 AE39 AD44 AF40 G23 AD43 AF39 AD42 AG44 J38 AD41 AG43 AE44 AG42 AE38 AE43 AG41 AE42 AG40 G26 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 3 7 (CL) 7 (CL) 3 7 (CL) 3 7 (CL) 4 VREF Group IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS I/O Pin Description PL21D PL21B VDD15 PL21C PL21A PL22D PL22B VDDIO7 PL22C PL22A PL23D PL23B VSS PL23C PL23A PL24D PL24B PL24C PL24A PL25D PL25B VDDIO7 PL25C PL25A PL26D PL26B VSS PL26C PL26A PL27D PL27B VDD15 PL27C PL27A PL28D PL28B VDDIO7 PL28C PL28A PL29D PL29B VSS -
ORCA ORSPI4 Data Sheet
Additional Function A11/PPC_A25
FTE1036 Pair L39C L40C L39T L40T L41C L42C L41T L42T L43C L44C L43T L44T L45C L46C L45T L46T L47C L48C L47T L48T L49C L50C L49T L50T L51C L52C L51T L52T L53C L54C L53T L54T L55C L56C -
VREF_7_03 RD_N/MPI_STRB_ N VREF_7_04 PLCK0C PLCK0T A10/PPC_A24 A9/PPC_A23 A8/PPC_A22 VREF_7_05 PLCK1C PLCK1T VREF_7_06 -
7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 4 7 (CL) 5 7 (CL) 5 7 (CL) 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 5 7 (CL) 6 7 (CL) 6 7 (CL) 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 -
235
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AE41 AG39 AF44 AH40 N38 AF43 AH39 AF42 AJ40 AF38 AF41 AJ39 AH44 AK42 G29 AH43 AK41 AH42 AK40 R7 AH41 AK39 AJ44 AJ43 AJ42 AM44 G32 AJ41 AM43 AK44 AL40 T38 AK43 AL39 AL44 AN43 AL43 AP43 AL42 AR43 AB1 AL41 AR42 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 6 7 (CL) 7 7 (CL) 7 7 (CL) 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 7 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 7 (CL) 8 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 VREF Group IO IO IO IO VDD15 IO IO IO IO VDDIO7 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO IO IO IO IO VSS IO IO I/O Pin Description PL29C PL29A PL30D PL30B VDD15 PL30C PL30A PL31D PL31B VDDIO7 PL31C PL31A PL32D PL32B VSS PL32C PL32A PL33D PL33B VDD15 PL33C PL33A PL34D PL34C PL35D PL35B VSS PL35C PL35A PL36D PL36B VDD15 PL36C PL36A PL37D PL37B PL37C PL37A PL38D PL38B VSS PL38C PL38A -
ORCA ORSPI4 Data Sheet
Additional Function A7/PPC_A21 A6/PPC_A20 A5/PPC_A19 WR_N/MPI_RW VREF_7_07 A4/PPC_A18 VREF_7_08 A3/PPC_A17 A2/PPC_A16 A1/PPC_A15 A0/PPC_A14 DP0 DP1 D8 VREF_6_01 -
FTE1036 Pair L55T L56T L57C L58C L57T L58T L59C L60C L59T L60T L61C L62C L61T L62T L63C L64C L63T L64T L65C L65T L67C L68C L67T L68T L69C L70C L69T L70T L71C L72C L71T L72T L73C L74C L73T L74T
236
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AM42 AN40 U7 AM41 AN39 AM40 AP40 AJ38 AM39 AP39 AP44 AN42 AD7 AR44 AN41 AP42 AT44 Y7 AP41 AT43 AU44 AV44 AM38 AU43 AV43 AU42 AW44 AD38 AT42 AY44 AR41 BB44 AC7 AR40 BA44 AU41 AR38 AT41 AT40 AG7 AT39 AG38 AR39 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 1 6 (BL) 2 6 (BL) 2 6 (BL) 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 2 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 6 (BL) 3 6 (BL) 3 6 (BL) 3 6 (BL) 4 6 (BL) 3 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 4 6 (BL) 6 (BL) 4 6 (BL) 4 6 (BL) 4 VREF Group IO IO VDD15 IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO VDDIO6 IO IO VSS IO VSS I I/O Pin Description PL39D PL39B VDD15 PL39C PL39A PL40D PL40B VDDIO6 PL40C PL40A PL41D PL41B VSS PL41C PL41A PL42D PL42B VDD15 PL42C PL42A PL43D PL43B VDDIO6 PL43C PL43A PL44D PL44B VSS PL44C PL44A PL45D PL45B VDD15 PL45C PL45A PL46D VDDIO6 PL46C PL47D VSS PL47C VSS PTEMP D9 D10 -
ORCA ORSPI4 Data Sheet
Additional Function
FTE1036 Pair L75C L76C L75T L76T L77C L78C L77T L78T L79C L80C L79T L80T L81C L82C L81T L82T L83C L84C L83T L84T L85C L86C L85T L86T L87C L88C L87T L88T L89C L89T L91C L91T -
VREF_6_02 D11 D12 VREF_6_03 D13 VREF_6_04 PLL_CK7C/HPPLL PLL_CK7T/HPPLL PTEMP
237
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AV29 AE7 BC33 BA42 AK7 AV42 AH38 BB43 BC42 AV32 BA43 BD42 BC41 AK38 BD41 BC40 AJ7 BD40 AW43 BA37 AV35 AY43 BB37 AW42 BC37 AN1 AY42 BD37 AW41 BA36 AL38 AV41 BB36 AY41 BC36 BA41 BD36 AU40 BA35 AN7 AU39 BB35 AW40 6 (BL) VREF Group VDDIO6 VDD15 IO VDD33 VSS VDD33 VDD15 IO IO VDDIO6 IO IO IO VSS IO IO VDD15 IO IO IO VDDIO6 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO IO IO IO IO VSS IO IO IO I/O Pin Description VDDIO6 VDD15 LVDS_R VDD33_FPGAPLL VSS VDD33_FPGAPLL VDD15 PB2A PB2C VDDIO6 PB2B PB2D PB3C VSS PB3D PB4C VDD15 PB4D PB5A PB5C VDDIO6 PB5B PB5D PB6A PB6C VSS PB6B PB6D PB7A PB7C VDD15 PB7B PB7D PB8A PB8C PB8B PB8D PB9A PB9C VSS PB9B PB9D PB10A -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair
LVDS_R DP2 PLL_CK6T/PPLL PLL_CK6C/PPLL VREF_6_05 DP3 VREF_6_06 D14 D15 D16 D17 D18 -
6 (BL) 5 6 (BL) 5 6 (BL) 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 5 6 (BL) 6 6 (BL) 6 6 (BL) 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 6 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 7
L93T L94T L93C L94C L96T L96C L98T L98C L99T L100T L99C L100C L101T L102T L101C L102C L103T L104T L103C L104C L105T L106T L105C L106C L107T L108T L107C L108C L109T
238
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank BC35 AV40 BD35 BA34 BB34 BA40 BC34 BB40 BD34 AV39 BA33 AW39 BB33 BB39 BA32 BA39 BB32 BC39 BC32 BD39 BD32 BB38 BA31 BA38 BB31 AW38 BC31 AY38 BD31 BC38 BA30 BD38 BB30 AW37 BC30 AY37 BD30 AW36 BA29 AY36 BB29 AW35 BC29 6 (BL) 7 6 (BL) 7 6 (BL) 7 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 8 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 9 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 10 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 6 (BL) 11 5 (BC) 1 5 (BC) 1 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PB10C PB10B PB10D PB11C PB11D PB12A PB12C PB12B PB12D PB13A PB13C PB13B PB13D PB14A PB14C PB14B PB14D PB15A PB15C PB15B PB15D PB16A PB16C PB16B PB16D PB17A PB17C PB17B PB17D PB18A PB18C PB18B PB18D PB19A PB19C PB19B PB19D PB20A PB20C PB20B PB20D PB21A PB21C D19 D20 D21 -
ORCA ORSPI4 Data Sheet
Additional Function VREF_6_07
FTE1036 Pair L110T L109C L110C L112T L112C L113T L114T L113C L114C L115T L116T L115C L116C L117T L118T L117C L118C L119T L120T L119C L120C L121T L122T L121C L122C L123T L124T L123C L124C L125T L126T L125C L126C L127T L128T L127C L128C L129T L130T L129C L130C L131T L132T
VREF_6_08 D22 D23 D24 VREF_6_09 D25 D26 D27 VREF_6_10 D28 D29 D30 VREF_6_11 D31 -
239
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AN38 AY35 BD29 AW34 BA28 AM7 AY34 BB28 AW33 BC28 AV17 BD28 BA27 AY33 BB27 AW32 BC27 AP38 AY32 BD27 AW31 BA26 AV20 AY31 BB26 AW30 BC26 AN44 AY30 BD26 AW29 BA25 AR7 AY29 BB25 AW28 BC25 AV21 AY28 BD25 AW27 BA24 AV7 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 1 5 (BC) 2 5 (BC) 2 5 (BC) 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 2 5 (BC) 3 5 (BC) 3 5 (BC) 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 3 5 (BC) 4 5 (BC) 5 (BC) 3 5 (BC) 4 5 (BC) 4 5 (BC) 4 VREF Group VSS IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO VSS I/O Pin Description VSS PB21B PB21D PB22A PB22C VDD15 PB22B PB22D PB23A PB23C VDDIO5 PB23D PB24C PB24B PB24D PB25A PB25C VDD15 PB25B PB25D PB26A PB26C VDDIO5 PB26B PB26D PB27A PB27C VSS PB27B PB27D PB28A PB28C VDD15 PB28B PB28D PB29A PB29C VDDIO5 PB29B PB29D PB30A PB30C VSS -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair L131C L132C L133T L134T L133C L134C L135T L136T L136C L138T L137C L138C L139T L140T L139C L140C L141T L142T L141C L142C L143T L144T L143C L144C L145T L146T L145C L146C L147T L148T L147C L148C L149T L150T -
VREF_5_01 PBCK0T PBCK0C VREF_5_02 VREF_5_03 PBCK1T PBCK1C -
240
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AY27 BB24 AW26 BC24 AT7 AY26 BD24 AW25 BA23 AV23 AY25 BB23 AW23 BC23 AV18 AY23 BD23 AW24 BA22 AT38 AY24 BB22 AW22 BD21 AV25 AY22 BC21 BD20 AV22 BC20 AY21 BB20 AU7 AW21 BA20 BA21 BD19 AV26 BB21 BC19 AY20 BB19 AV24 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 4 5 (BC) 5 5 (BC) 5 5 (BC) 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 5 5 (BC) 6 5 (BC) 6 5 (BC) 5 (BC) 6 5 (BC) 6 5 (BC) 6 5 (BC) 6 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 5 (BC) 7 5 (BC) 7 5 (BC) 7 5 (BC) 7 VREF Group IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO VSS IO IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO VSS IO IO IO VDD15 IO IO IO IO VDDIO5 IO IO IO IO VSS I/O Pin Description PB30B PB30D PB31A PB31C VDD15 PB31B PB31D PB32A PB32C VDDIO5 PB32B PB32D PB33A PB33C VSS PB33B PB33D PB34A PB34C VDD15 PB34B PB34D PB35A PB35C VDDIO5 PB35B PB35D PB36C VSS PB36D PB37A PB37C VDD15 PB37B PB37D PB38A PB38C VDDIO5 PB38B PB38D PB39A PB39C VSS -
ORCA ORSPI4 Data Sheet
Additional Function VREF_5_04 VREF_5_05 VREF_5_06 VREF_5_07 -
FTE1036 Pair L149C L150C L151T L152T L151C L152C L153T L154T L153C L154C L155T L156T L155C L156C L157T L158T L157C L158C L159T L160T L159C L160C L162T L162C L163T L164T L163C L164C L165T L166T L165C L166C L167T L168T -
241
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AW20 BA19 AY19 BD18 AW19 BC18 AY18 BB18 AW18 BA18 AY17 BD17 AV27 AW17 BC17 AY16 BB17 AW16 BA17 BD13 BD16 BC13 BC16 BB16 AV30 BA16 BD12 BD14 BC12 BD15 BC15 BC14 BC11 AV33 BD7 BD8 BB1 BB2 AV15 BD6 BC8 AV38 BC7 5 (BC) 7 5 (BC) 7 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 8 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 9 5 (BC) 10 5 (BC) 10 5 (BC) 10 5 (BC) 10 5 (BC) 10 5 (BC) 10 VREF Group IO IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO VDD33 VSS VDD33 I I I I VDDGB I VSS I I/O Pin Description PB39B PB39D PB40A PB40C PB40B PB40D PB41A PB41C PB41B PB41D PB42A PB42C VSS PB42B PB42D PB43A PB43C PB43B PB43D PB44A PB44C PB44B PB44D PB45C VSS PB45D PB46A PB46C PB46B PB46D PB47C PB47D VDD33_FPGAPLL VSS VDD33_FPGAPLL SPARE_1 RESETN TRISTN TESTMD1N VDDGB TESTMD0N VSS PDN -
ORCA ORSPI4 Data Sheet
Additional Function
FTE1036 Pair L167C L168C L169T L170T L169C L170C L171T L172T L171C L172C L173T L174T L173C L174C L175T L176T L175C L176C L177T L178T L177C L178C L180T L180C L181T L182T L181C L182C L184T L184C -
VREF_5_08 VREF_5_09 VREF_5_10 PLL_CK5T/PPLL PLL_CK5C/PPLL -
242
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank BD5 BD4 BD3 BC3 AV13 BB7 BC6 BC4 BC5 AW8 AW15 AY15 BA15 BB15 AY14 AW10 BA14 AV10 BB14 AW12 AW13 AY13 BA13 BB13 AY12 AW14 BA12 AV12 BB12 BC9 AW11 AY11 BA11 BB11 AV14 AY10 BC10 BA10 BB10 BD9 AW9 AY9 BA9 VREF Group I I I I I I O O O VSS VDDOB O O VDDOB I VSS I VDD_ANA VDDIB VSS VDDOB O O VDDOB I VSS I VDD_ANA VDDIB VSS VDDOB O O VDDOB VDD_ANA I VSS I VDDIB VSS VDDOB O O I/O Pin Description ATREFCLK TESTCLK BTREFCLK TSTAT1B TSTAT0B TSCLKB RSTAT1B RSTAT0B RSCLKB VSS VDDOB_D HDOUTP_D HDOUTN_D VDDOB_D HDINP_D VSS HDINN_D VDD_ANA VDDIB_D VSS VDDOB_C HDOUTP_C HDOUTN_C VDDOB_C HDINP_C VSS HDINN_C VDD_ANA VDDIB_C VSS VDDOB_B HDOUTP_B HDOUTN_B VDDOB_B VDD_ANA HDINP_B VSS HDINN_B VDDIB_B VSS VDDOB_A HDOUTP_A HDOUTN_A -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair
HSP_1 HSN_1 HSP_2 HSN_2 HSP_3 HSN_3 HSP_4 HSN_4 HSP_5 HSN_5 HSP_6 HSN_6 HSP_7 HSN_7
243
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank BB9 AV8 AY8 BD10 BA8 BB8 AW7 AY7 BA7 AV11 AW4 AU6 AW3 AV6 AV3 T6 AV9 T7 AV2 AY2 AR6 AW2 BC1 AT4 BC2 BB5 AT3 BB6 AU38 AV16 AR5 BC22 BA1 AR4 AY1 AP5 W6 AW1 W7 AP4 AV1 BC43 AN6 VREF Group VDDOB VDD_ANA I VSS I VDDIB I I O O I I I I I VDD33 I/O VDD33 I I I/O I VSS I VSS I I I VDD15 VDD15 O VSS O O O O VDD33 O VDD33 O O VSS O I/O Pin Description VDDOB_A VDD_ANA HDINP_A VSS HDINN_A VDDIB_A REFCLKP REFCLKN REXTN REXT ATSTAT1N ATSTAT0N ATSTAT1P ATSTAT0P ATSCLKN VDD33 ALVCTAP5 VDD33 ATSCLKP BTSCLKN BLVCTAP5 BTSCLKP VSS BTSTAT1N VSS BTSTAT0N BTSTAT1P BTSTAT0P VDD15 VDD15 BRSTAT1N VSS BRSTAT0N BRSTAT1P BRSTAT0P BRSCLKN VDD33 ARSCLKN VDD33 BRSCLKP ARSCLKP VSS ARSTAT1N -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair
HSP_8 HSN_8 HSP_9 HSN_9 R1C R2C R1T R2T R3C R3T R4C R4T R5C R6C R5T R6T R7C R8C R7T R8T R9C R10C R9T R10T R11C
244
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank BA5 BC44 AN5 BA6 AV19 AV28 AU1 AP1 BD1 AR1 BA2 AB6 AB7 AM6 BD2 BA4 AM5 BA3 AM4 AV31 AY4 AM3 AV34 AY3 AL5 BD11 AW5 AL4 AW6 AF6 AL3 AF7 AV5 AL2 AV4 BD22 AK6 BD33 AU5 AK5 AU4 AV36 AK4 VREF Group O VSS O O VDD15 VDD15 I I VSS I I VDD33 VDD33 O VSS O O O O VDD15 O O VDD15 O O VSS O O O VDD33 O VDD33 O O O VSS O VSS O O O VDD15 VDDA_SPIA I/O Pin Description ARSTAT0N VSS ARSTAT1P ARSTAT0P VDD15 VDD15 RESLO RESHI VSS REF14 REF10 VDD33 VDD33 BTDAT15N VSS BTDAT14N BTDAT15P BTDAT14P BTDAT13N VDD15 BTDAT12N BTDAT13P VDD15 BTDAT12P BTDAT11N VSS BTDAT10N BTDAT11P BTDAT10P VDD33 BTDAT9N VDD33 BTDAT8N BTDAT9P BTDAT8P VSS BTCTLN VSS BTDCLKN BTCTLP BTDCLKP VDD15 VDDA_SPIA -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair R12C R11T R12T R13C R14C R13T R14T R15C R16C R15T R16T R17C R18C R17T R18T R19C R20C R19T R20T R21C R22C R21T R22T -
245
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AV37 AK3 AU3 AJ6 BD43 AU2 AJ5 AJ4 AH6 AT6 AJ3 AH7 AT5 AH5 AT2 BD44 AH4 AT1 AH3 AY5 AR3 AH2 AY6 AP3 AG6 AR2 AG5 AP2 AF1 AL6 AN4 AL7 AG4 AN3 AG3 AM2 AF3 AM1 AF2 AL1 AF4 AK1 AE6 VREF Group VDD15 VSS O O VSS O O O VDD33 O O VDD33 O O O VSS O O O VDD15 O O VDD15 O I I I I I/O VDD33 I VDD33 I I I I I I I I I/O I I I/O Pin Description VDD15 VSS BTDAT7N BTDAT6N VSS BTDAT7P BTDAT6P BTDAT5N VDD33 BTDAT4N BTDAT5P VDD33 BTDAT4P BTDAT3N BTDAT2N VSS BTDAT3P BTDAT2P BTDAT1N VDD15 BTDAT0N BTDAT1P VDD15 BTDAT0P BRDCLKN BRDAT15N BRDCLKP BRDAT15P BLVCTAP1 VDD33 BRDAT14N VDD33 BRDAT13N BRDAT14P BRDAT13P BRDAT12N BRDAT11N BRDAT12P BRDAT11P BRDAT10N BLVCTAP2 BRDAT10P BRDAT9N -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair
R23C R24C R23T R24T R25C R26C R25T R26T R27C R28C R27T R28T R29C R30C R29T R31T R32C R33C R32T R33T R34C R35C R34T R35T R36C R37C R36T R37T R38C R38T R39C
246
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AK2 AE5 AJ2 AE4 AN2 AE3 AP6 AJ1 AP7 AD6 AH1 AD5 AG2 AD4 AG1 AD3 AF5 AC6 AE2 AC5 AE1 AC4 AD2 AC3 AD1 W1 V1 AC1 U1 AC2 AA1 AA2 AB2 AA3 AB3 AA4 Y1 V2 Y2 U2 Y3 AB5 Y4 VREF Group I I I I I/O I VDD33 I VDD33 I I I I I I I I/O I I I I I I I I VSS VDDA_SPIB O VSS O O O O O O O O O O O O O O I/O Pin Description BRDAT8N BRDAT9P BRDAT8P BRCTLN BLVCTAP3 BRCTLP VDD33 BRDAT7N VDD33 BRDAT6N BRDAT7P BRDAT6P BRDAT5N BRDAT4N BRDAT5P BRDAT4P BLVCTAP4 BRDAT3N BRDAT2N BRDAT3P BRDAT2P BRDAT1N BRDAT0N BRDAT1P BRDAT0P VSS VDDA_SPIB ATDAT15N VSS ATDAT15P ATDAT14N ATDAT14P ATDAT13N ATDAT12N ATDAT13P ATDAT12P ATDAT11N ATDAT10N ATDAT11P ATDAT10P ATDAT9N ATDAT8N ATDAT9P -
ORCA ORSPI4 Data Sheet
Additional Function
FTE1036 Pair R40C R39T R40T R41C R41T R42C R43C R42T R43T R44C R45C R44T R45T R46C R47C R46T R47T R48C R49C R48T R49T R50C R50T R51C R51T R52C R53C R52T R53T R54C R55C R54T R55T R56C R57C R56T
247
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AB4 W2 AA5 W3 Y5 W4 AA6 W5 Y6 T1 V3 R1 U3 T2 V4 R2 U4 T3 R4 R3 R5 T4 U5 U6 P1 V5 P2 V6 T5 M3 P3 M4 P4 P5 N1 P6 N2 R6 N3 N5 N4 N6 M1 VREF Group O O O O O O O O O O O O O O O O O O O O O VSS VDDA_SPIC VSS I I I I I/O I I I I I I I I I/O I I I I I I/O Pin Description ATDAT8P ATCTLN ATDCLKN ATCTLP ATDCLKP ATDAT7N ATDAT6N ATDAT7P ATDAT6P ATDAT5N ATDAT4N ATDAT5P ATDAT4P ATDAT3N ATDAT2N ATDAT3P ATDAT2P ATDAT1N ATDAT0N ATDAT1P ATDAT0P VSS VDDA_SPIC VSS ARDCLKN ARDAT15N ARDCLKP ARDAT15P ALVCTAP1 ARDAT14N ARDAT13N ARDAT14P ARDAT13P ARDAT12N ARDAT11N ARDAT12P ARDAT11P ALVCTAP2 ARDAT10N ARDAT9N ARDAT10P ARDAT9P ARDAT8N -
ORCA ORSPI4 Data Sheet
Additional Function
FTE1036 Pair R57T R58C R59C R58T R59T R60C R61C R60T R61T R62C R63C R62T R63T R64C R65C R64T R65T R66C R67C R66T R67T R68C R69C R68T R69T R70C R71C R70T R71T R72C R73C R72T R73T R74C R75C R74T R75T R76C
248
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank L2 M2 L3 G1 M6 K1 M5 K2 K3 J1 J3 J2 H3 H1 L5 H2 L4 G2 K4 G3 J4 L6 K5 F1 L7 E1 D4 H4 D1 K6 F2 J5 C4 G4 E2 E5 G5 F3 G9 J6 F4 H5 F6 VREF Group I I I I/O I I I I I I I I I/O I I I I I I I I VDDA_SPID VSS I I I VSS O O O I/O I/O I/O I/O I/O VSS I/O I/O VSS I/O I/O I/O VDDH I/O Pin Description ARCTLN ARDAT8P ARCTLP ALVCTAP3 ARDAT7N ARDAT6N ARDAT7P ARDAT6P ARDAT5N ARDAT4N ARDAT5P ARDAT4P ALVCTAP4 ARDAT3N ARDAT2N ARDAT3P ARDAT2P ARDAT1N ARDAT0N ARDAT1P ARDAT0P VDDA_SPID VSS TSTAT1A TSTAT0A TSCLKA VSS RSTAT1A RSTAT0A RSCLKA PMIA17 PMIA16 PMIA15 PMIA14 PMIA13 VSS PMIA12 PMIA11 VSS PMIA10 PMIA9 PMIA8 VDDH -
ORCA ORSPI4 Data Sheet
Additional Function
FTE1036 Pair R77C R76T R77T R78C R79C R78T R79T R80C R81C R80T R81T R82C R83C R82T R83T R84C R85C R84T R85T -
249
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank E3 D2 E4 D3 G13 G6 G15 H6 H7 C1 G7 C3 F5 E6 K7 C2 G10 M7 P7 D7 D5 G12 C5 D6 G8 F7 C6 E7 G14 D8 B3 E8 B4 B9 A3 C7 A4 G16 C8 A9 B5 C10 D10 VREF Group I/O I/O I/O VREF VSS I/O VSS I/O I/O I/O VDDH I/O I/O I/O VSS I VDDH VSS VSS I/O I/O VDDH I/O I/O I/O I/O I/O I/O VDDH I/O I/O I/O I/O I/O I/O I/O I/O VDDH I/O I/O I/O I/O VREF I/O Pin Description PMIWN PMIRN PMIA7 REFI_1 VSS PMIA6 VSS PMIA5 PMIA4 PMIA3 VDDH PMIA2 PMIA1 PMIA0 VSS EXT_1K VDDH VSS VSS PMID35 PMID34 VDDH PMID33 PMID32 PMID31 PMID30 PMID29 PMID28 VDDH PMID27 PMID26 PMID25 PMID24 PMID23 PMID22 PMID21 PMID20 VDDH PMID19 PMID18 PMID17 PMID16 REFI_2 -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair
250
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank F8 B10 D9 A10 E9 B11 C9 C11 J7 F9 D11 B6 E11 B7 C12 N7 A5 D12 B8 B12 A12 C13 D13 A7 B13 A8 A13 A6 C14 F11 D14 G11 B14 F10 A14 E10 C15 F12 D15 E12 B15 F13 A15 VREF Group I/O I/O I/O I/O I/O I/O I/O I/O VDDH I/O I/O I/O I/O I/O I/O VDDH I/O I/O I/O I/O VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Description PMIK PMIKN PMID15 PMID14 PMID13 PMID12 PMID11 PMID10 VDDH PMID9 PMID8 PMID7 PMID6 PMID5 PMID4 VDDH PMID3 PMID2 PMID1 PMID0 REFI_3 PMIC PMICN PMIQ35 PMIQ34 PMIQ33 PMIQ32 PMIQ31 PMIQ30 PMIQ29 PMIQ28 PMIQ27 PMIQ26 PMIQ25 PMIQ24 PMIQ23 PMIQ22 PMIQ21 PMIQ20 PMIQ19 PMIQ18 PMIQ17 PMIQ16 -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair
251
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank E13 C16 F14 D16 E14 B16 F15 A16 E15 C17 F16 D17 E16 B17 F17 A17 E17 A18 D18 B18 C18 A19 B19 E18 G17 F18 C19 AY39 E21 D19 F21 E19 L1 F19 C20 G18 E23 D20 F23 E20 AY40 E24 F20 VREF Group I/O I/O I/O VREF I/O I/O I/O VDDA_PLL I/O VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD33 VDD33 IO VDDIO1 IO IO VDD15 IO IO IO IO VSS IO IO VDDIO1 IO IO IO IO VDD15 IO IO I/O Pin Description MCREFCLK SPARE_2 PMIQ15 REFI_4 PMIQ14 PMIQ13 PMIQ12 VDDA_PLL PMIQ11 VSS PMIQ10 PMIQ9 PMIQ8 PMIQ7 PMIQ6 PMIQ5 PMIQ4 PMIQ3 PMIQ2 PMIQ1 PMIQ0 VDD33_FPGAPLL VDD33_FPGAPLL PT47D VDDIO1 PT47C PT46D VDD15 PT46B PT46C PT46A PT45D VSS PT45C PT44D VDDIO1 PT44B PT44C PT44A PT43D VDD15 PT43B PT43C -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair
1 (TC) 7 1 (TC) 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 7 1 (TC) 8 1 (TC) 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8
PLL_CK2C/PPLL PLL_CK2T/PPLL VREF_1_07 -
L185C L185T L187C L188C L187T L188T L189C L189T L191C L192C L191T L192T L193C L194C L193T
252
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank F24 B20 L44 F22 A20 G22 C21 G21 E26 D21 F26 B21 BB3 E25 A21 F25 D22 M38 E28 E22 F28 C22 G24 E29 B22 F29 C23 BB4 E27 D23 F27 B23 R38 A23 C24 G27 C31 D24 D31 B24 BB41 E31 A24 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 8 1 (TC) 9 1 (TC) 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 9 1 (TC) 10 1 (TC) 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 10 1 (TC) 1 1 (TC) 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 VREF Group IO IO VSS IO IO IO IO VDDIO1 IO IO IO IO VDD15 IO IO IO IO VSS IO IO IO IO VDDIO1 IO IO IO IO VDD15 IO IO IO IO VSS IO IO VDDIO1 IO IO IO IO VDD15 IO IO I/O Pin Description PT43A PT42D VSS PT42B PT42C PT42A PT41D VDDIO1 PT41B PT41C PT41A PT40D VDD15 PT40B PT40C PT40A PT39D VSS PT39B PT39C PT39A PT38D VDDIO1 PT38B PT38C PT38A PT37D VDD15 PT37B PT37C PT37A PT36D VSS PT36C PT35D VDDIO1 PT35B PT35C PT35A PT34D VDD15 PT34B PT34C -
ORCA ORSPI4 Data Sheet
Additional Function VREF_1_08 VREF_1_09 VREF_1_10 VREF_1_01 -
FTE1036 Pair L194T L195C L196C L195T L196T L197C L198C L197T L198T L199C L200C L199T L200T L201C L202C L201T L202T L203C L204C L203T L204T L205C L206C L205T L206T L207C L207T L209C L210C L209T L210T L211C L212C L211T
253
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank F31 C25 V7 E30 D25 F30 B25 G28 E32 A25 F32 C26 BB42 D33 D26 E33 B26 V38 F33 A26 G33 C27 E34 D27 F34 B27 E35 A27 F35 C28 AA7 C35 D28 D35 B28 A37 A28 B37 C29 E36 D29 F36 B29 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 1 1 (TC) 2 1 (TC) 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 2 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 3 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 4 VREF Group IO IO VSS IO IO IO IO VDDIO1 IO IO IO IO VDD15 IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PT34A PT33D VSS PT33B PT33C PT33A PT32D VDDIO1 PT32B PT32C PT32A PT31D VDD15 PT31B PT31C PT31A PT30D VSS PT30B PT30C PT30A PT29D PT29B PT29C PT29A PT28D PT28B PT28C PT28A PT27D VSS PT27B PT27C PT27A PT26D PT26B PT26C PT26A PT25D PT25B PT25C PT25A PT24D -
ORCA ORSPI4 Data Sheet
Additional Function
FTE1036 Pair L212T L213C L214C L213T L214T L215C L216C L215T L216T L217C L218C L217T L218T L219C L220C L219T L220T L221C L222C L221T L222T L223C L224C L223T L224T L225C L226C L225T L226T L227C L228C L227T L228T L229C L230C L229T L230T L231C
VREF_1_02 VREF_1_03 -
254
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank AA38 C37 A29 D37 A30 E37 B30 F37 D30 A38 C30 B38 A31 C38 B31 D38 A32 E38 B32 F38 C32 E43 D32 E44 A34 A33 F44 B34 F43 B33 G38 F41 C33 F42 C34 F40 G39 D34 G40 A35 A43 H40 B35 1 (TC) 4 1 (TC) 4 1 (TC) 4 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 5 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 1 (TC) 6 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 1 0 (TL) 2 0 (TL) 1 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 VREF Group VSS IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VSS IO IO IO IO VDDIO0 IO IO IO IO VDD15 IO IO IO IO VSS IO IO I/O Pin Description VSS PT24B PT24C PT24A PT23D PT23B PT23C PT23A PT22D PT22B PT22C PT22A PT21D PT21B PT21C PT21A PT20D PT20B PT20C PT20A PT19D PT19B PT19C PT19A PT18D VSS PT18B PT18C PT18A PT17D VDDIO0 PT17B PT17C PT17A PT16D VDD15 PT16B PT16C PT16A PT15D VSS PT15B PT15C -
ORCA ORSPI4 Data Sheet
Additional Function -
FTE1036 Pair L232C L231T L232T L233C L234C L233T L234T L235C L236C L235T L236T L237C L238C L237T L238T L239C L240C L239T L240T L241C L242C L241T L242T L243C L244C L243T L244T L245C L246C L245T L246T L247C L248C L247T L248T L249C L250C
VREF_1_04 PTCK1C PTCK1T PTCK0C PTCK0T VREF_1_05 VREF_1_06 MPI_RTRY_N MPI_ACK_N VREF_0_01 M0 M1 MPI_CLK -
A21/MPI_BURST_N L249T
255
Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank H39 A36 P38 B36 C36 G19 G41 D36 G42 A39 A44 A40 A41 U38 G43 A42 G44 B39 G25 B40 B41 B1 H44 B42 H43 C39 C40 D39 J42 D40 J41 E39 F39 C41 J40 D41 J39 E41 E42 C43 H42 D43 H41 0 (TL) 2 0 (TL) 2 0 (TL) 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 2 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 3 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 4 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 5 0 (TL) 6 0 (TL) 6 0 (TL) 6 0 (TL) 6 VREF Group IO IO VDDIO0 IO IO VDD15 IO IO IO IO VSS IO IO VDDIO0 IO IO IO IO VDD15 IO IO VSS IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I/O Pin Description PT15A PT14D VDDIO0 PT14C PT13D VDD15 PT13B PT13C PT13A PT12D VSS PT12C PT11D VDDIO0 PT11B PT11C PT11A PT10D VDD15 PT10C PT9D VSS PT9B PT9C PT9A PT8D PT8C PT7D PT7B PT7C PT7A PT6D PT6C PT5D PT5B PT5C PT5A PT4D PT4C PT3D PT3B PT3C PT3A M2 M3
ORCA ORSPI4 Data Sheet
Additional Function
FTE1036 Pair L250T L251C L251T L253C L254C L253T L254T L255C L255T L257C L258C L257T L258T L259C L259T L261C L262C L261T L262T L263C L263T L265C L266C L265T L266T L267C L267T L269C L270C L269T L270T L271C L271T L273C L274C L273T L274T
VREF_0_02 MPI_TEA_N VREF_0_03 D0 TMS A20/MPI_BDIP_N A19/MPI_TSZ1 A18/MPI_TSZ0 D3 VREF_0_04 D1 D2 VREF_0_05 TDI TCK VREF_0_06 -
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Lattice Semiconductor
Table 87. 1036 ftSBGA Pin Table (Continued)
FTE1036 VDDIO Ball Bank C44 D44 K38 K39 K40 K41 0 (TL) 6 0 (TL) 6 VREF Group IO IO O IO IO VDD33 I/O Pin Description PT2D PT2C PCFG_MPI_IRQ PCCLK PDONE VDD33_FPGAPLL
ORCA ORSPI4 Data Sheet
Additional Function PLL_CK1C/PPLL PLL_CK1T/PPLL CFG_IRQ_N/MPI_I RQ_N CCLK DONE -
FTE1036 Pair L275C L275T -
Note: All differential pairs use adjacent balls.
257
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Package Information
Package Thermal Characteristics Summary
There are three thermal parameters that are in common use: JA, JC, and JC. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow.
JA
This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.):
TJ - TA JA = -----------------Q
(1)
where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power. Experimentally, JA is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip's heater resistor, the chip's temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that JA is expressed in units of C/W.
JC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance and it is defined by:
JC = TJ - TC ------------------Q
(2)
where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the JA measurements described above, besides the other parameters measured, an additional temperature reading, TC, is made with a thermocouple attached at top-dead-center of the case. JC is also expressed in units of C/W.
JC
This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is defined by:
TJ - TC JC = ------------------Q
(3)
The parameters in this equation have been defined above. However, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates JC from JC. JC is a true thermal resistance and is expressed in units of C/W.
JB
This is the thermal resistance from junction to board. It is defined by:
TJ - TB JB = -----------------Q
(4)
where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters on the right-hand side have been defined above. This is considered a true thermal resistance, and the measure258
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
ment is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. Note that JB is expressed in units of C/W and that this parameter and the way it is measured are still being discussed by the JEDEC committee.
FPSC Maximum Junction Temperature
Once the power dissipated by the FPSC has been determined, the maximum junction temperature of the FPSC can be found. This is needed to determine if speed derating of the device from the 85 C junction temperature used in all of the delay tables is needed. Using the maximum ambient temperature, TAmax, and the power dissipated by the device, Q (expressed in C), the maximum junction temperature is approximated by: TJmax = TAmax + (Q * JA)
Package Thermal Characteristics
The thermal characteristics of the 1036-ball ftSBGA and the 1156-ball fpBGA used for the ORSPI4 are available at the Thermal Management section of the Lattice Semiconductor web site at www.latticesemi.com.
Heat Sink Vendors for BGA Packages
The estimated worst-case power requirements for the ORSPI4 is in the 8 W to 10 W range. Consequently, for most applications an external heat sink will be required. Table 88 lists, in alphabetical order, heat sink vendors who advertise heat sinks aimed at the BGA market.
Table 88. Heat Sink Vendors
Vendor Aavid Thermalloy Chip Coolers IERC R-Theta Sanyo Denki Wakefield Thermal Solutions Location Concord, NH Warwick, RI Burbank, CA Buffalo, NY Torrance, CA Pelham, NH Phone (603) 224-9988 (800) 227-0254 (818) 842-7277 (800) 388-5428 (310) 783-5400 (800) 325-1426
Package Parasitics
The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics.
Figure 102. Package Parasitics
LSW PAD N RW LSL
Pad N
C1 C2 LML Circuit Board Pads
Package Pads
LMW CM
PAD N + 1 LSW RW C1 LSL C2
Pad N+1
259
Lattice Semiconductor Package Outline Drawings
ORCA ORSPI4 Data Sheet
Package Outline Drawings for the 1036-ball ftSBGA and the 1156-ball fpBGA used for the ORSPI4 are available in the Package Diagrams section of the Lattice Semiconductor web site at www.latticesemi.com.
260
Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Ordering Information
ORSPI4 - X XXXXXX X XX
Device Family Speed Grade Optional Suffix Blank = Production ES = Engineering Samples Grade C = Commercial I = Industrial Package FTE1036 = 1036-ball ftSBGA (Thermally Enhanced Fine-Pitch Thin BGA) FE1036 = 1036-ball fpSBGA (Thermally Enhanced Fine-Pitch BGA) - Replaced by FTE1036 F1156 = 1156-ball fpBGA (Fine-Pitch BGA) FN1156 = Lead-Free1156-ball fpBGA (Fine-Pitch BGA)
Table 89. Device Type Options
Device ORSPI4 Voltage 1.5 V internal 3.3 V/2.5 V/1.8 V/ 1.5 V I/O
Table 90. Commercial Ordering Information1
Device Family Part Number ORSPI4-3FTE1036C ORSPI4-2FTE1036C ORSPI4-1FTE1036C ORSPI4-3FE1036C ORSPI4 ORSPI4-1FE1036C ORSPI4-3F1156C ORSPI4-2F1156C ORSPI4-1F1156C
2
Speed Grade 3 2 1 3 2 1 3 2 1
Package Type ftSBGA
Ball Count 1036
Grade C C C C
ORSPI4-2FE1036C2
2
fpSBGA
1036
C C C
fpBGA
1156
C C
Table 91. Industrial Ordering Information1
Device Family Part Number ORSPI4-2FTE1036I ORSPI4-1FTE1036I ORSPI4 ORSPI4-2FE1036I ORSPI4-2F1156I ORSPI4-1F1156I
2
Speed Grade 2 1 2 1 2 1
Package Type ftSBGA fpSBGA fpBGA
Ball Count 1036 1036 1156
Grade I I I I I I
ORSPI4-1FE1036I2
Table 92. Pb-free Commercial Ordering Information1
Device Family ORSPI4 Part Number ORSPI4-3FN1156C ORSPI4-2FN1156C ORSPI4-1FN1156C Speed Grade 3 2 1 Pb-free fpBGA 1156 Package Type Ball Count Grade C C C
261
Lattice Semiconductor
Table 93. Pb-free Industrial Ordering Information1
Device Family ORSPI4 Part Number ORSPI4-2FN1156I ORSPI4-1FN1156I Speed Grade 2 1
ORCA ORSPI4 Data Sheet
Package Type Pb-free fpBGA
Ball Count 1156
Grade I I
1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -3XXXXXC is also marked with the industrial grade -2XXXXXI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only. 2. Convert to FTE package per PCN#16A-07.
Revision History
Date - July 2004 Version - 02.0 Previous Lattice releases. Phase-Locked Loops description has been updated. ORSPI Transmit FPGA/Embedded Core Interface description has been updated. SPIA Core Transmit FPGA Interface in 32-Bit Mode. SPIA Core Transmit FPGA Interface in 64-Bit Mode, and Table 4. SPIA Core Transmit FPGA Interface in 128-Bit Mode have been updated. Link Disable section has been updated. TX DPRAM section has been updated. Port Credit Field Update Flow Chart has been added and the description has been updated. Calendar Programming section has been updated to "After programming the calendar memory, the TX_CAL_MEM_SEL bit is set to '0'." SPIA Core Receive FPGA Interface in 32-Bit Mode has been updated. RDI Block description has been updated. Far End Loopback Setup section has been added. ORSPI4 QDRII Memory Controller Block Diagram has been updated. FPGA/Embedded Core Signals has been updated. ORSPI4 Memory Controller Interface to FPGA - Write Timing Diagram has been updated. ORSPI4 Memory Controller Interface to QDRII: 4-Word Burst Mode has been updated. ORSPI4 Memory Controller Interface to FPGA - Read Timing Diagram has been updated. Memory Controller Instruction Latency section has been updated. Memory Map has been updated. ORSPI4 Post configuration Standby Current has been added. ORSPI4 SERDES Worst Case Power Table has been updated with footnote 2. Supported Data Rates has been updated. SPI4.2 Data Interface has been added." Timing Reference Points with Respect to Clock Edge has been updated. Data Path Interface Timing for Static Alignment has been updated. Status Path Interface OIF-SPI4-02.2 Specification Timing (Reference) has been updated. Status Path Interface ORSPI4 Timing in Centered (OIF) Mode has been updated. Status Channel Reference Points with Respect to Clock Edge has been updated. Status Path Interface ORSPI4 Timing in Legacy Mode has been updated. Channel Output Jitter (3.125 Gbits/s) has been updated. Channel Output Jitter (2.5 Gbits/s) has been updated." Memory Controller Input/Output Timing Specification has been added. Memory Controller Output Timing Specification has been added. Memory Controller Input Timing Specification has been added. Change Summary
262
Lattice Semiconductor
Date October 2004 Version 03.0
ORCA ORSPI4 Data Sheet
Change Summary Datasheet is now Final Status for production release of the device. Clock Rates under High Performance Memory Controller for Interface to External Buffer Memory has been updated to 175MHz DDR performance has been updated to 175MHz in the introduction section. FPGA Logic Overview section has been updated. Recommended Operating Conditions has been updated. ORSPI4 Post-Configuration Stabdby CurrentTable has been updated. ORSPI4 Combined SPIA and SPIB Worst Case Power Table has been updated. ORSPI4 QDR Memory Controller Worst Case Power Table has been updated. ORSPI4 SERDES Worst Case Power Table has been updated with footnote 2. Supported Data Rates Table has been updated. System Timing Reference Points has been updated. SPI4.2 Timing Points with Respect to Clock Edge has been added. SPI4.2 Data Interface Table has been updated. SPI4.2 Receive Timing Points with Respect to Clock Edge has been added." SPI4.2 Receive Data Interface Timing has been updated. Data Path Interface Timing for Static Alignment has been updated. Data Path Parameters for Dynamic Alignment has been updated. Status Channel Reference Points with Respect to Clock Edge (LVDS and LVTTL I/Os) has been updated. Status Path Interface ORSPI4 Timing in Centered (OIF) Mode Status Channel Reference Points with Respect to Clock Edge (Edge Aligned Legacy Mode) has been updated. Status Path Interface ORSPI4 Timing in Legacy Mode has been updated. Channel Output Jiffer (3.125 Gbits/s) has been updated. Channel Output Jitter (2.5 Gbits/s) has been updated. HSTL Class I and II section has been updated. HSTL Class II DC Operating Specifications has been updated. Supported Data Rtes (36-Bit QDR-II, 32 bit Considered Data) Table has been updated. Memory Controller Output Timing Specifications has been updated. Memory Controller Input Timing Specifications have been updated. Memory Controller Input Timing Specifications have been updated. Recommended Power Supply Connections section has been updated. Recommended Power Supply Filtering Scheme section has been updated. Commercial Ordering Information Table and Industrial Ordering Information Table have been updated for production release of the ORSPI4. Released 1156-fpBGA Pb-free devices. Added 1036-ball ftSBGA information per PCN#16A-07 (package conversion from 1036fpSBGA to 1036-ftSBGA).
February 2005
04.0
April 2005 October 2007
05.0 06.0
263

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